At 11:38 AM 11/30/2005, you wrote:
Am a newbie to layout and trying out the electric tool for layout. I
am using a
bulk driven configuration in my circuit. How do i do this in electric. When i
use the mocmos library ... all the p-wells are connected to gnd and n-Wells to
vdd irrespective of what signals i give to the well contact.( i need to give
clock to some of the p-wells). How do i avoid this?? Is there a provision for
using the twin-well process so that this can be avoided. Could not find any
documentation about using the bulk driven configuration in
electric.Please Help
Electric does not maintain an explicit knowledge of the well
connectivity. However, you can make presumptions about it by placing
well or substrate contacts and wiring them appropriately. Note that
the "mocmos" technology is a dual-well process that places both
p-well and n-well in addition to p-select and n-select on
transistors. When emitting layers (in GDS or CIF) all layers are
emitted, but half of them are ignored by the fab process.
The only problem that you will have with this nonstandard form of
wiring is that some tools may get confused (notably the ERC well
checker). Other than that, you should be able to do your designs.
-Steven Rubin
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