I'm trying to run an ALS simulation of a basic logic circuit (half-adder).
I can successfully simulate the circuit with a AND2 and XOR2 gate, but if I
toggle the output ports of the two gates to get a NAND2 and XNOR2, the VHDL
compiler complains:
Generating VHDL from 'cell 'half_adder_logicNEW{sch}'' ... Done, created
cell 'half_adder_logicNEW{vhdl}'
Compiling VHDL in cell 'half_adder_logicNEW{vhdl}' ...***** UNRESOLVED
REFERENCES *****
xnor2, 1 time(s)
Done, created cell 'half_adder_logicNEW{net.als}'
Simulating netlist in cell 'half_adder_logicNEW{net.als}'
ERROR: Model 'XNOR2' not found, simulation aborted
The output VHDL is:
-- VHDL automatically generated from cell 'half_adder_logicNEW{sch}'
entity half_adder_logicNEW is port(In1, In2: in BIT; Cout, S: out BIT);
end half_adder_logicNEW;
architecture half_adder_logicNEW_BODY of half_adder_logicNEW is
component nand2 port(a1, a2: in BIT; y: out BIT);
end component;
component xnor2 port(a1, a2: in BIT; y: out BIT);
end component;
begin
and_0: nand2 port map(In1, In2, Cout);
xor_0: xnor2 port map(In1, In2, S);
end half_adder_logicNEW_BODY;
I'm fairly new to VHDL (I'm not a circuit designer by trade ;-), so I'm not
sure if this is a problem with my circuit or a problem with Elecric.
Any pointers would be welcomed.
I'm running Electric 8.04 currently.
Thanks!
--kan--
--
Kevin A. Noll, KD4WOZ
CCIE, CCDP
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