I would like to do N, where N is larger than 4, correlators on the FPGA
in order to do code acquisition for code division multiplexing.  I would
also
like to do beam steering experiments on four channels.  All involve
multiplications and the lower the latency, the better.

Then the question becomes how MUCH ram is burned in this scheme?  Is it
onerous?  We are not anywhere near the fill up point in the Cyclone yet
are we? Can we get a link to this paper instead of just an announcement?

The last time I looked, an HDTV receiver is not a low power device. Why
would we care unless the heat load can't be born by the device running
at full tilt?

Bob




-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Behalf
Of David Willmore
Sent: Monday, March 14, 2005 6:21 PM
To: Eric Blossom
Cc: Ilia Mirkin; John Gilmore; discuss-gnuradio@gnu.org
Subject: Re: [Discuss-gnuradio] signals/atsc question


> Altera has a nice app note on synthesizing multipliers by burning up
> RAM.  As I recall it's not too hard to generate a multiplier that does
> 12-bit*16-bit in two cycles.  We're clocked at 64 MHz, though 128 MHz
> should be possible with some hacking.
>
> If you're decimated down to 8MS/s complex and want to use an 8-tap FIR
> interpolation filter you need to peform 8M * 2 * 8 = 128M multiplies
> per second.  This should be possible using a pair of RAM based
> multipliers.  I don't recall how much RAM it takes.  It's non-trivial.

Sorry, everyone, I'm still quite lagged--though at least I'm caught up
to gnuradio traffic from this month (and this year!).

My quick comments on this scheme is that you'd be wasting power and
gates (ram as well) on a multiplier designed for low latency.  Latency
isn't much of an issue here, is it?  Just implement the FIR filter as
a bitwise multiplication pipeline and you'll use a lot fewer gates, use
less power and get the same effect.  You will have a much higher latency,
but for TV reception, what's a few us?

Cheers,
David n0ymv


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