Tim - On Mon, May 02, 2005 at 01:46:48PM +0930, Tim Ansell wrote: > So where do we request free samples from :P
Good question. I'd be happy with a data sheet, for the moment.
I'm in the low-latency business, so this chip _may_ be useless to me.
> The question is how would you get this into a computer? If we round it
> up to 16 bits, it makes 4.6 Gigabytes per second. Would a FPGA even be
> able to keep up? Could people a lot smarter then me, discuss how this
> chip could even possibly be used?
Look at the table again (as corrected by Krzysztof? I can't verify
because lists.gnu.org is currently refusing port 80 connections):
>Parameter GaAs SiGe
>
>Maximum clock frequency > 5 GHz > 15 GHz
>SINAD (signal to noise+distortion) > 70 dB > 110 dB
>Eff. resolution bits at 2.5 GHz carrier:
>10 MHz BW 14 bits 18 bits
>100 MHz BW 11 bits 14 bits
So what you need coming out is N bits at something over
twice the bandwidth. For the SiGe chip, that's 14 bits at > 200 MS/s.
Even with generous provision for filter guard bands and compatibility
with maximum accuracy, you have 20 bits at 300 MS/s, well within reach
of a modern FPGA.
The patent looks -- well, too obvious to be patentable [*]. They seem
to be trying to patent a mixer followed by a sigma-delta converter, in
particular the case where the same frequency is used for the mixer LO
and the sigma-delta modulator clock.
- Larry
[*] but then, what do I know. I'm an engineer, so I must not count
as someone "skilled in the art".
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