On Thursday 06 April 2006 15:11, Marcus Leech wrote: > > Also, I think getting 32.768 MHz from 4Mhz with a PLL would be pretty > > difficult (if not impossible) > > Given that you haven't looked into the PLLs on the FPGA, it's rather too > early > to conclude that you couldn't synthesize 32.768Mhz from the 4Mhz > reference clock that's already on the USRP. > Given reasonable dividers for both reference and VFO, I can't see why > synthesizing > 32.768Mhz would be all that difficult. I can understand why you might > want to > use a dedicated oscillator--you don't have to muck with the FPGA. > But asserting that > it's "difficult (if not impossible)" is hard to support if you haven't > looked into it.
According to the datasheet the PLL can only do m/n where m is between 1 and 32 and n is between 1 and 4. Therefore I don't see how it's possible. I was only guessing before, but I just checked the datasheet and it seems impossible. You could get close with a Stratix II.. 4 * 498/62 = 32.129 MHz Whereas a Cyclone can only do m/n where m is 1 to 32 and n is 1 to 4. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
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