Hi Eric. Thanks for your help. It all works exactly how you said. I was
enabling the correct pins using "usrp.source_c(0, 64)" - the code I pasted
"usrp.sink_c(0, 64)" was a blind copy-paste from Oussama's email. Sorry
about the confusion.
All I was missing was the " u._write_oe(1, 0xffff, 0xffff) ". I put that it
and it all worked nicely.
I have another question. I'm outputting two pieces of information on my 2
BasicRX daughter boards - (1) 3 clocks and (2) the USB data. The Verilog
code looks as follows:
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
.debug_0(rx_debugbus),.debug_1(usbdata_out),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),
.debug_3(usbclk,clk64,clk128),
//
.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
Now I'm getting some signals on my oscilloscope that I'm not happy with.
1) First of all, the clk64 signal looks like a sine - wave. The frequency is
64MhZ according to my oscilloscope. I was expecting a square wave. Is this
correct?
2) I get nothing from clk128 - it may just not be connected. Is this
correct?
3) The usbclk is also outputting a signal that looks like a sine-wave at
around 50MHz. Is this correct?
4) The USB data signals look very very unsteady. They look nothing like a
square wave or a sine wave - almost somewhere in between with slow rising
edges and then fast drops to 0.
I'll explain briefly what I am trying to do. Essentially I've got another
FPGA board that I want to get the output from the USRP board to be
trasferred onto. Essenitally, I want the I,Q pairs that go to the USB on the
USRP board to go to the daughterboard pins so that I can sample them on this
second FPGA board.
I've written some python code to output 1, and 0s onto the daughter board
pins (that's why I needed the previous help - thanks again Eric). The
python code is basically a loop that outputs 0x0 and 0xffff alternately to
the daughter board pins. My oscilloscope shows a nice clean square wave
which comes out at about 3KHz when I remove all delays (delays made with
python's sleep). I guess this speed is the fastest at which the python code
can be interpreted, and the signal sent up the usb to the FPGA and then to
the daughter board pins. This has led to me to believe that, perhaps I'm
having a problem of speed - perhaps the USB data coming out of the FPGA is
changing too fast for a clear wave to show up on the daughter-board pins.
Would this be a correct analysis?
Any help would be greatly appreciated as I'm hitting a bit of a wall now.
Thanks a lot for the already received help.
Andrew
----- Original Message -----
From: "Eric Blossom" <[EMAIL PROTECTED]>
To: "Andrew Borg" <[EMAIL PROTECTED]>
Cc: <Discuss-gnuradio@gnu.org>
Sent: Tuesday, September 26, 2006 5:35 PM
Subject: Re: [Discuss-gnuradio] Daughter board pins
> On Tue, Sep 26, 2006 at 03:15:16PM +0100, Andrew Borg wrote:
>
>> Hi Oussama. I managed to get the signals I want out of my daughter
>> board (BasicRX) on RxA. So thanks a lot for your help (and by proxy
>> to Eric too!). However, I have one more problem. I need to get some
>> other signals out from the FPGA on my other daughterboard that is on
>> the board marked RxB. The Verilog code I can handle - no problems
>> there. What I am unsure about is the python code. So far I have the
>> following code which outputs the signals I need from RxA:
>
>>
>> u = usrp.sink_c(0, 64)
>> u._write_oe(0, 0xffff, 0xffff)
>
> Note that this is output enabling the pins on the TX_A daugterboard.
> Is that what you wanted? I hope so ;)
> It's the TX_A because you opened the sink_c, and you're passing 0 as
> the "which" argument to _write_oe
>
>
> Assuming you've got two Basic Rx d'boards installed, one on the A side
> and one on the B side, you'll want:
>
> u = usrp.source_c(0, 64) # note that we're opening the source
> u._write_oe(0, 0xffff, 0xffff)
> u._write_oe(1, 0xffff, 0xffff)
> u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A | bmFR_DEBUG_EN_RX_B)
>
>
>> u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A)
>>
>> The above is basically what you sent me. Now if I change the last line to
>> :
>>
>
>
>> then I still get the signals I need from RxA but still nothing from
>> RX_B (I've changed the Verilog code as required - I understand that
>> part fine). I also tried adding u._write_oe(1, 0xffff, 0xffff) but
>> it still does not work. This latest try is a stab in the dark and
>> I'm afraid to go further without asking because of the worrying
>> comments before the _write_oe function!! I was tempted to move the
>> daughter board to a TX slot but was afraid of cooking the board.
>
> Being afraid of cooking the board is a good thing to have on your mind ;)
> The Tx and Rx boards are _NOT_ interchangable. Don't try it.
>
> If this doesn't help, you might want to take another look at your
> verilog. Perhaps you're connecting your debug output to the wrong
> pins?
>
>
> debug_0 is TX_A
> debug_1 is RX_A
> debug_2 is TX_B
> debug_3 is RX_B
>
>
>
> wire [15:0] reg_0,reg_1,reg_2,reg_3;
> master_control master_control
> ( .master_clk(clk64),.usbclk(usbclk),
>
>
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
> .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
> .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
> .enable_tx(enable_tx),.enable_rx(enable_rx),
> .interp_rate(interp_rate),.decim_rate(decim_rate),
> .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
> .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
> .tx_empty(tx_empty),
> //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
> .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
>
>
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
> .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
>
>
> Eric
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