I actually get a very strange behavior now. Every time I rerun my program , the output of the logic analyzer changes. But the output that comes up the most often is the one I described before where bit 1 toggles, and bit 5 is asserted (sometimes) .
What I am trying to do is to get some delay measurements in the following way: if 12 bit input (say rx_a) is larger than a certain threshold, than I assert a signal in a register. So for this reason I am trying to see what's the digital "value" of the noise input in order to have an idea on how to set the threshold. Has anyone done any such thresholding measurements? Is there a good or 'basic' threshold that I could use for my measurements? Any suggestion would be greatly appreciated. Thank you, Oussama. On 11/17/06, Oussama Sekkat <[EMAIL PROTECTED]> wrote:
On 11/17/06, Brian Padalino <[EMAIL PROTECTED]> wrote: > > On 11/17/06, Oussama Sekkat <[EMAIL PROTECTED]> wrote: > > > > Ok. > > I fixed it now by making it a source instead. Thanks. > > My output reading from the logic analyzer is now the following > constant 16 > > bit value: 0000 1111 1100 0011 > > This seems to me a too high of a value since I shouldn't be receiving > any > > signal. On top of that, none of the bits are toggling, which doesn't > make > > sense if it was just noise. > > Any ideas on what's going on here? > > Would it be worth while to try to see if you can use Altera's Signal > Tap software (internal FPGA logic analyzer) to help out? I don't know > the M4k usage in the part with the design, but there should be enough > to help a little debug - right? Does the FPGA have a convenient JTAG > connection to it? I don't think the FPGA has a JTAG connection to it. I did the same tests agains, but I used a Basic RX daugterboard instead of the previous LFRX. Now I get the following output: all bits are 0 except bit 5 and bit 1 toggles. This output seems to make a little more sense to me. Does it look like a reasonable output ? Thank you for your time. > Thanks again, > > > > Oussama. > > Brian >
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