We'd have to compile the blocks for the SPE's.
Hopefully the compiler does a decent job of extracting parallelism
from the code without too much help. Of course we could hand tune the
filter kernels like we do today.
The scheduler and behind-the-scenes block interconnect/buffering would
need to be modified, but that's pretty well abstracted away from the
user's view of the world.
We'd need to build some tools that would allow us to measure
performance on the SPE and allow us to do feedback based assignment of
subsets of blocks in a graph to the SPEs. I think this would be an
iterative process. That is, partition the graph across the SPEs. Run
your test case. Measure. Repeat.
Sounds like fun.
And yes, I think we could get the HDTV receiver running in real time ;)
Eric
I am looking to build a new computer (or buy) for graduate school and I
would like my platform to be able to have real-time image-processing
capabilities. Do you know of any other platforms where that is possible
right now? Also, what do you think of the possibility of developing another
peripheal that would act like a Cell BE board that would be used in
conjunction with the USRP?
Newell
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