Trond:
Tuning the down-converter on the DBS-RX card consists of programming the
values of 2 dividers. The R divider divides down the reference clock
frequency (4 MHz, which derives from the 64 MHz board clock). The N
divider divides down the LO frequency. The R divider has a range from 2
to 256, the N divider from 256 to 32768. The Max2118 phase locks the
divide LO frequency to the divided reference clock frequency, or:
LO = N*(Refclk_Freq/R)
However, the PLL in the Max2118 is unstable if you divide down the
reference clock frequency to below 250 kHz, this effectively limits the
frequency resolution at which you can command the LO frequency.
Additionally, the error in the board clock at 64 MHz will produce a
frequency error in the LO frequency of tens of kHz at L1. I would
suggest passing a sine wave at 1.57542 GHz through the DBS-RX and USRP
(set the digital down-convert frequency to 0), and observing where the
frequency appears in the PSD of your samples. You can then use the
resulting frequency to command the digital down-convert stage of the
USRP to mix L1 precisely to baseband. I will formally submit the C++
driver after I get it commented out, if you want the version I have
working now I can forward it to you.
Greg Heckler
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