Brian Padalino wrote:
On 8/3/07, Zhuocheng Yang <[EMAIL PROTECTED]> wrote:
You haven't really modeled what the board is doing properly, so your
code is probably doing exactly what it should in the circumstances
you're giving to it. You should get a dump of the raw packets
George's server is trying to send to the USRP and run them through
your simulation.
This basically solved the problem. It turns out that the start and end
burst flags were swapped in the host side code. This obviously created
problems :) By using live packets, we were able to pinpoint it. Once
the host followed spec, the problem was solved and we are now moving on
with life :)
As a side note, we also tested out spacing like you suggested using the
oscope and timestamps. The FPGA is properly waiting for the timestamp
to reach and transmitting at that point. Using the oscope we checked
proper spacing according to our timestamps and it is correct.
Moreover, I think you may have some signed/unsigned issues. I
haven't been able to recreate the problem you specifically see, but
it could possibly be related to another problem that I see when I run
your code - specifically when the time has become negative (in a
signed sense).
Right, we agree with this. This is something we also need to fix.
Thanks for this heads up :)
- George
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