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Would anyone be interested in an additional decimation stage after the
CIC and the halfband filters? The usable bandwidth is ~25-50% of the
actual post decimation sample rate, an additional decimation stage (no
filtering, just a plain decimation) would allow the sample rate pushed
across the USB to be decreased while discarding the unused bandwidth. I
am going to pursue this myself and wondered if I should post any
Verilog changes I make. --
 [EMAIL PROTECTED] NASA Goddard Space Flight Center AETD - Mission Engineering and Systems Analysis Component and Hardware Systems Branch Mail Code 596, Greenbelt Rd. Greenbelt, MD 20771 (301) 286-6565 (301) 286-3823 (fax) |
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