Hi Eric,
Thank you for your help.

You are right 0.384Hz is nothing to worry about :) I misunderstood the 'm'

Regarding the frequency I finally found where the problem comes from:

After the gmsk modulation (blks2.gmsk_mod) I have to scale the value (for
example by multiplying it by 8000) before sending it to the USRP to get the
resulting signal centered at the right frequency. If don't do it the output
signal is shifted... I assume some minimum signal level is needed in the
FPGA blocks to work correctly.

Rgds,


On Sat, Apr 19, 2008 at 5:20 PM, Eric Blossom <[EMAIL PROTECTED]> wrote:

> On Fri, Apr 18, 2008 at 07:38:15PM -0400, Wireless Monster wrote:
> > After doing some experiments I came out with another more important
> > problem...
> >
> > Instead of my previous frequency that gave some residual, I tried the
> > integer frequency 926M, so I get:
> >
> > Using TX d'board A: Flex 900 Tx MIMO B
> > r.baseband_freq = 930M
> > r.dxc_freq      = -4M
> > r.residual_freq = 0
> > r.inverted      = False
> >
> > The issue is that on the spectrum analyzer I get the signal centered at
> 930
> > and not 926M.
> >
> > Any clue why the r.dxc offsset is not working? I check the 'tune'
> function
> > and it should do...
> >
> > Thanks!
>
>
> If you use usrp_siggen.py does the signal end up where you expect?
> If so, the problem's somewhere in your code.
>
> I'm not very good at mind reading...
>
> Eric
>
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