Chuck,
I have a question regarding the comment you made in an earlier email on
the subject:
You said:
-------------
Now my question: Is it possible to tune the usrp so the carrier is at
+.31 Mhz ? (band center at 3, from -.2 to 6.2Mhz?) Then we could run
the cpll at 6.4 or 8Msps and get another big performance boost, maybe.
Right now the pll at 19.2 Mhz (6.4 * 3) is an expensive part. Eric, I
guess the bit timing loop would work at 24Mhz (8 * 3).
-------------
I don't see where the 19.2 MHz figure comes about...
My understanding is that when the USRP is tuned to the center of the
6MHz band, the signal that goes through the USB is
u(t) = z(t) exp(-j fsym/4 +j phi)
where fsym = 1/Tsym = 10.76 MHz (so fsym/4=2.69MHz), and
z(t)= x(t)+j x(t) * g(t)
representing the complex lowpass equivalent of the VSB signal.
z(t) is a complex signal with non-zero frequencies in
[-3+2.69,3+2.69]=[-0.31,5.69]MHz
So the signal u(t) needs to be sampled at 6 Complex-Msps, which is what
you do (sampling it at 6.4 Complex-Msps, or as Eric wants at 8
complex-Msps).
Now my understanding is that you need to upsample u(t) by a factor of 2
(in software, ie, making it a 12.8 Complex-Msps signal) and then
run on it the complex pll where the nominal VCO frequency is
fsym/4 = 2.69MHz.
The "out" signal of the cPLL will be the real signal x(t) sampled at
12.8 Msps which is fine since this is the original 8-PAM signal after
Nyquist sampling.
So, what is the 19.2 MHz frequency you are referring to?
The way I see it the cPLL works at 12.8 complex-Msps.
Am I missing something?
Thanks
Achilleas
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