Brian, Can AGC be implemented in code, on the verilog side using the FPGA?
Thanks -Benjamin uoting Brian Padalino <[EMAIL PROTECTED]>: > On Mon, Dec 1, 2008 at 10:53 PM, <[EMAIL PROTECTED]> wrote: > > > > I am trying to achieve a goal of controlling the AGC, please help. > > > > Here is what I have so far, for the automatic gain control (AGC): > > > > I have found in the module adc_interface (which is in > > fpga\sdr_lib\adc_interface) a comment about level sensing for the AGC. > > > > I am assuming the module rssi and module adc_interface is where the AGC is > > controlled? > > > > If not where do I go about turning on or off the AGC. The rssi is used to > sense > > the signal strength in the fpga and that is feedback to the ADC which > controls > > the AGC, is that correct? > > I don't believe there is any AGC actually going on at all. Please see here: > > http://gnuradio.org/trac/ticket/66 > > > After I know how to turn on and off the AGC, how do I adjust the gain of > the > > amplifier? > > You need to familiarize yourself with the gain settings of the > different daughterboards and how their gains are controlled. > > The Python db code is probably a good place to start looking. > > > If I wanted to make a block diagram, or refer to a schematic that involves > the > > AGC, where should I start? > > > > Is the AGC located before the ADC, and the ADC is contained in the fpga, > right? > > The ADC is an external chip. The data feeds into the FPGA where it is > then processed. > > > Thank you so much for your time and help, > > Good luck. > > Brian > _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
