Hi,
attached is a somewhat larger patch for the FPGA firmware.
The patch changes the following:
- stable timestamp, timestamp is latched on the last sample that goes into the
packet, so in case no overrun happens, timestamp goes up reliably 126 times
decimation rate.
- channel buffer is emptied when an overrun happens, avoids multiple overruns
in short succession
- tx timestamp wrap around, range is divided into 2^31 past and 2^31 future
timestamps.
- dropped flag is set
- overrun flag is set
- tag is set to the tag of the last sent package
- rssi value is transmitted in a logarithmic representation
- waiting on fifos is shortened based on the fact that these get filled and
emptied at a fixed rate. If the reader is faster than the writer, than the
fifo should reach zero level when the reader finishes.
The patches have successfully been tested with 1tx1rx on usrp rev4. Loopback
works, overrun and underrun reporting works, drops are reported as well.
Regards,
Stefan
--
Stefan Brüns / Bergstraße 21 / 52062 Aachen
phone: +49 241 53809034 mobile: +49 151 50412019
=== modified file 'usrp/fpga/inband_lib/chan_fifo_reader.v'
--- usrp/fpga/inband_lib/chan_fifo_reader.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/inband_lib/chan_fifo_reader.v 2009-02-24 21:01:19 +0000
@@ -1,7 +1,7 @@
module chan_fifo_reader
(reset, tx_clock, tx_strobe, timestamp_clock, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
- underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
+ underrun, tx_empty, debug, rssi, threshhold, rssi_wait, drop, tagline) ;
input wire reset ;
input wire tx_clock ;
@@ -19,6 +19,8 @@
input wire [31:0] rssi;
input wire [31:0] threshhold;
input wire [31:0] rssi_wait;
+ output reg drop;
+ output reg [3:0] tagline;
output wire [14:0] debug;
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
@@ -37,6 +39,7 @@
// Header format
`define PAYLOAD 8:2
+ `define TAG 12:9
`define ENDOFBURST 27
`define STARTOFBURST 28
`define RSSI_FLAG 26
@@ -52,6 +55,8 @@
reg trash;
reg rssi_flag;
reg [31:0] time_wait;
+ reg [32:0] time_to_wait;
+ reg [3:0] tag_save;
always @(posedge tx_clock)
begin
@@ -68,6 +73,8 @@
trash <= 0;
rssi_flag <= 0;
time_wait <= 0;
+ time_to_wait <= 0;
+ drop <= 0;
end
else
begin
@@ -86,10 +93,10 @@
begin
reader_state <= HEADER;
rdreq <= 1;
- underrun <= 0;
end
+
if (burst == 1 && pkt_waiting == 0)
- underrun <= 1;
+ underrun <= ~underrun;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
@@ -102,10 +109,7 @@
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
- if (fifodata[`STARTOFBURST] == 1
- && fifodata[`ENDOFBURST] == 1)
- burst <= 0;
- else if (fifodata[`STARTOFBURST] == 1)
+ if (fifodata[`STARTOFBURST] == 1 && fifodata[`ENDOFBURST] == 0)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
@@ -115,19 +119,27 @@
skip <= 1;
reader_state <= IDLE;
rdreq <= 0;
+ burst <= 0;
end
else
begin
payload_len <= fifodata[`PAYLOAD] ;
+ tag_save <= fifodata[`TAG];
read_len <= 0;
rdreq <= 1;
- reader_state <= TIMESTAMP;
+ if( fifodata[`STARTOFBURST] == 0)
+ begin
+ reader_state <= WAIT;
+ timestamp <= 32'hFFFFFFFF;
+ end else
+ reader_state <= TIMESTAMP;
end
end
TIMESTAMP:
begin
timestamp <= fifodata;
+ time_to_wait <= ({1'b1, fifodata} - {1'b0, timestamp_clock});
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
@@ -137,32 +149,31 @@
// Decide if we wait, send or discard samples
WAIT:
begin
+ rdreq <= 0;
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
+ // Let's send it
+ if ( (time_wait>=time_to_wait[31:0])
+ || timestamp == 32'hFFFFFFFF )
+ begin
+ if (rssi <= threshhold || rssi_flag == 0)
+ begin
+ trash <= 0;
+ reader_state <= WAITSTROBE;
+ tagline <= tag_save;
+ end
+ end
// Outdated
- if ((timestamp < timestamp_clock) ||
- (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
- begin
- trash <= 1;
- reader_state <= IDLE;
- skip <= 1;
- end
- // Let's send it
- else if (timestamp == timestamp_clock
- || timestamp == 32'hFFFFFFFF)
- begin
- if (rssi <= threshhold || rssi_flag == 0)
- begin
- trash <= 0;
- reader_state <= WAITSTROBE;
- end
- else
- reader_state <= WAIT;
- end
- else
- reader_state <= WAIT;
+ else if ( (time_to_wait[31:0] >= 32'h7fffffff) ||
+ (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag) )
+ begin
+ trash <= 1;
+ reader_state <= IDLE;
+ skip <= 1;
+ drop <= ~drop;
+ end
end
// Wait for the transmit chain to be ready
@@ -186,7 +197,13 @@
// Send the samples to the tx_chain
SEND:
begin
- reader_state <= WAITSTROBE;
+ if( read_len+1 == payload_len )
+ begin
+ reader_state <= IDLE;
+ skip <= 1;
+ end
+ else
+ reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
=== modified file 'usrp/fpga/inband_lib/channel_ram.v'
--- usrp/fpga/inband_lib/channel_ram.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/inband_lib/channel_ram.v 2009-02-24 20:50:24 +0000
@@ -95,7 +95,7 @@
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
- assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
+ assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)) | (wr_addr >= 7'd64);
always @(posedge txclk)
if (reset)
nb_packets <= 0;
=== modified file 'usrp/fpga/inband_lib/packet_builder.v'
--- usrp/fpga/inband_lib/packet_builder.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/inband_lib/packet_builder.v 2009-02-24 21:23:39 +0000
@@ -10,13 +10,16 @@
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
+ output reg chan_flush,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
+ input fx2_empty,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] underrun);
+ input [NUM_CHAN:0] underrun, input [NUM_CHAN:0] drop,
+ input [3:0] tagline);
// States
@@ -44,12 +47,20 @@
reg [8:0] read_length;
reg [8:0] payload_len;
reg timestamp_complete;
+ reg [31:0] timestamp_save;
+ reg [31:0] timestamp_chan_ready;
reg [3:0] check_next;
+ reg [NUM_CHAN:0]chan_empty_last;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
+ wire [5:0]rssi_law;
+ rssi_lin_law lin_law( .lin( true_rssi[10:1]), .law( rssi_law ) );
+ reg [NUM_CHAN:0] drop_last;
+ reg [NUM_CHAN:0] underrun_last;
+
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
@@ -57,8 +68,6 @@
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
- assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
- ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
@@ -71,55 +80,69 @@
timestamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
+ chan_empty_last <= ~0;
+ drop_last <= 0;
+ underrun_last <= 0;
end
- else case (state)
+ else begin
+ if (chan_empty_last != chan_empty)
+ timestamp_chan_ready <= #1 timestamp_clock; // FIXME: should be one per channel
+ chan_empty_last <= chan_empty;
+
+ case (state)
`IDLE: begin
- chan_rdreq <= #1 0;
- //check if the channel is full
- if(~chan_empty[check_next])
- begin
- if (have_space)
- begin
- //transmit if the usb buffer have space
- //check if we should send
- if (ready_to_send)
- state <= #1 `HEADER1;
-
- overrun[check_next] <= 0;
- end
- else
- begin
- state <= #1 `IDLE;
- overrun[check_next] <= 1;
- end
+ chan_rdreq <= #1 0;
+ //check if the channel has enough data
+ if(~chan_empty[check_next])
+ begin
+ if (overrun[check_next] && ~fx2_empty)
+ chan_flush <= 1; // drain
+ else if (have_space)
+ begin
+ //transmit if the usb buffer has space
+ state <= #1 `HEADER1;
+ check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
+ end else begin // have_space == 0
+ state <= #1 `IDLE;
+ overrun[check_next] <= 1;
+ end
rd_select <= #1 check_next;
+ end else begin // chan_empty[] == 0
+ check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
+ chan_flush <= 0;
end
- check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
- fifodata[`TAG] <= #1 0;
+ fifodata[`TAG] <= #1 tagline;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
+ timestamp_save <= timestamp_chan_ready;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
- fifodata[`RSSI] <= #1 true_rssi[5:0];
+ fifodata[`RSSI] <= #1 rssi_law;
fifodata[`BURST] <= #1 0;
- fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
+ fifodata[`DROPPED] <= #1 (check_next == 0) ? 1'b0 :
+ ( drop[true_channel] == drop_last[true_channel]) ? 1'b0 : 1'b1;
+ fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 :
+ ( underrun[true_channel] == underrun_last[true_channel]) ? 1'b0 : 1'b1;
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
+
+ if (check_next != 0) overrun[true_channel] <= #1 0;
+ drop_last[true_channel] = drop[true_channel];
+ underrun_last[true_channel] = underrun[true_channel];
end
`TIMESTAMP: begin
- fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]);
+ fifodata <= #1 (timestamp_complete ? timestamp_save[31:16] : timestamp_save[15:0]);
timestamp_complete <= #1 ~timestamp_complete;
if (~timestamp_complete)
@@ -147,6 +170,7 @@
state <= `IDLE;
end
endcase
+ end
end
endmodule
=== modified file 'usrp/fpga/inband_lib/rx_buffer_inband.v'
--- usrp/fpga/inband_lib/rx_buffer_inband.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/inband_lib/rx_buffer_inband.v 2009-02-24 21:29:09 +0000
@@ -34,6 +34,10 @@
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [3:0] tagline_0,
+ input wire [3:0] tagline_1,
+ input wire [31:0] timestamp_clock,
+ input wire [1:0] tx_drop,
input wire [1:0] tx_underrun
);
@@ -49,14 +53,6 @@
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
-
- // Time counter
- reg [31:0] timestamp_clock;
- always @(posedge rxclk)
- if (reset)
- timestamp_clock <= 0;
- else
- timestamp_clock <= timestamp_clock + 1;
// USB side fifo
wire [11:0] rdusedw;
@@ -90,6 +86,7 @@
assign fifodata_il[0] = (sel)?ch_1:ch_0;
assign fifodata_il[1] = (sel)?ch_3:ch_2;
+ wire fx2_empty;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
@@ -99,12 +96,14 @@
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
- .rdempty ( ),
+ .rdempty ( fx2_empty ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
- assign have_pkt_rdy = (rdusedw >= 12'd256);
+ // packet builder is faster than the GPIF, so as long as WR is asserted,
+ // fifo fill level will go up
+ assign have_pkt_rdy = (rdusedw >= 12'd256) || (rdusedw >= 12'd8 && WR);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
@@ -117,8 +116,13 @@
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
+ wire [3:0] tagline_sel;
+ wire chan_flush;
+
+ assign tagline_sel = (rd_select == 0) ? tagline_0 :
+ (rd_select == 1) ? tagline_1 : 3'b0;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builder (
.rxclk ( rxclk ),
.reset ( reset ),
.timestamp_clock ( timestamp_clock ),
@@ -126,14 +130,16 @@
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
+ .chan_flush ( chan_flush ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
+ .fx2_empty ( fx2_empty ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .underrun(tx_underrun));
+ .underrun(tx_underrun),.drop(tx_drop),.tagline(tagline_sel));
// Detect overrun
always @(posedge rxclk)
@@ -144,11 +150,6 @@
else if(clear_status)
rx_overrun <= 1'b0;
-
- // FIXME: what is the purpose of these two lines?
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
-
wire cmd_empty;
always @(posedge rxclk)
@@ -169,11 +170,13 @@
begin : generate_channel_fifos
wire rdreq;
+ wire flush;
assign rdreq = (rd_select == i) & chan_rdreq;
+ assign flush = (rd_select == i) & chan_flush;
fifo_1kx16 rx_chan_fifo (
- .aclr ( reset ),
+ .aclr ( reset | flush ),
.clock ( rxclk ),
.data ( fifodata_il[i] ),
.rdreq ( rdreq ),
=== modified file 'usrp/fpga/inband_lib/tx_buffer_inband.v'
--- usrp/fpga/inband_lib/tx_buffer_inband.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/inband_lib/tx_buffer_inband.v 2009-02-24 21:36:45 +0000
@@ -17,8 +17,12 @@
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
- input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
- output wire [1:0] tx_underrun,
+ input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
+ input wire [31:0] timestamp_clock,
+ output wire [1:0] tx_underrun,
+ output wire [1:0] tx_drop,
+ output wire [3:0] tx_tagline_0,
+ output wire [3:0] tx_tagline_1,
//system stop
output wire stop, output wire [15:0] stop_time);
@@ -28,19 +32,12 @@
genvar i ;
/* These will eventually be external register */
- reg [31:0] timestamp_clock ;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
-
- always @(posedge txclk)
- if (reset)
- timestamp_clock <= 0;
- else
- timestamp_clock <= timestamp_clock + 1;
/* Connections between tx_usb_fifo_reader and
@@ -53,6 +50,10 @@
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
+ wire [NUM_CHAN:0] chan_drop;
+ wire [3:0] chan_tagline [NUM_CHAN:0];
+ assign tx_tagline_0 = chan_tagline[0];
+ assign tx_tagline_1 = chan_tagline[1];
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
@@ -83,7 +84,6 @@
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
@@ -105,6 +105,7 @@
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
+ assign tx_drop[i] = chan_drop[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
@@ -120,7 +121,8 @@
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
- .threshhold(threshhold), .rssi_wait(rssi_wait));
+ .threshhold(threshhold), .rssi_wait(rssi_wait), .drop(chan_drop[i]),
+ .tagline(chan_tagline[i]) );
end
endgenerate
=== modified file 'usrp/fpga/megacells/fifo_1kx16.v'
--- usrp/fpga/megacells/fifo_1kx16.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/megacells/fifo_1kx16.v 2009-02-24 20:50:24 +0000
@@ -7,18 +7,21 @@
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// 8.1 Build 163 10/28/2008 SJ Web Edition
// ************************************************************
-//Copyright (C) 1991-2006 Altera Corporation
+//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
-//functions, and any output files any of the foregoing
+//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
@@ -80,13 +83,13 @@
.full (sub_wire4)
// synopsys translate_off
,
- .sclr (),
- .almost_full ()
+ .almost_full (),
+ .sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.almost_empty_value = 504,
+ scfifo_component.almost_empty_value = 252,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
@@ -105,7 +108,7 @@
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "252"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -120,10 +123,14 @@
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
@@ -133,7 +140,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "252"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
@@ -171,5 +178,6 @@
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
=== modified file 'usrp/fpga/megacells/fifo_1kx16_bb.v'
--- usrp/fpga/megacells/fifo_1kx16_bb.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/megacells/fifo_1kx16_bb.v 2009-02-24 20:50:24 +0000
@@ -7,17 +7,20 @@
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// 8.1 Build 163 10/28/2008 SJ Web Edition
// ************************************************************
-//Copyright (C) 1991-2006 Altera Corporation
+//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
-//functions, and any output files any of the foregoing
+//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
@@ -57,7 +60,7 @@
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "252"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -72,10 +75,14 @@
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
@@ -85,7 +92,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "252"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
@@ -123,5 +130,6 @@
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
=== added file 'usrp/fpga/sdr_lib/rssi_lin_law.v'
--- usrp/fpga/sdr_lib/rssi_lin_law.v 1970-01-01 00:00:00 +0000
+++ usrp/fpga/sdr_lib/rssi_lin_law.v 2009-02-24 21:38:49 +0000
@@ -0,0 +1,20 @@
+module rssi_lin_law (
+ input [9:0] lin,
+ output reg [5:0] law );
+
+ always @(lin)
+ begin
+ casex(lin)
+ 10'b1xxxxxxxxx : law <= {3'b111,lin[8:6]};
+ 10'b01xxxxxxxx : law <= {3'b110,lin[7:5]};
+ 10'b001xxxxxxx : law <= {3'b101,lin[6:4]};
+ 10'b0001xxxxxx : law <= {3'b100,lin[5:3]};
+ 10'b00001xxxxx : law <= {3'b011,lin[4:2]};
+ 10'b000001xxxx : law <= {3'b010,lin[3:1]};
+ 10'b0000001xxx : law <= {3'b001,lin[2:0]};
+ // 10'b0000000xxx : law = {3'b000,lin[2:0]};
+ default : law <= {3'b000,lin[2:0]};
+ endcase
+ end
+
+endmodule
=== modified file 'usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v'
--- usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v 2008-04-30 02:52:31 +0000
+++ usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v 2009-02-24 21:43:22 +0000
@@ -129,12 +129,17 @@
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
+wire [1:0] tx_drop;
+wire [3:0] tx_tagline [0:1];
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
+ .tx_drop(tx_drop),
+ .tx_tagline_0(tx_tagline[0]),
+ .tx_tagline_1(tx_tagline[1]),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
@@ -153,6 +158,7 @@
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+ .timestamp_clock(timestamp_clock),
.stop(stop), .stop_time(stop_time));
`ifdef TX_DUAL
@@ -211,6 +217,15 @@
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ reg [31:0] timestamp_clock;
+ always @(posedge clk64)
+ if (rx_dsp_reset)
+ timestamp_clock <= 0;
+ else
+ timestamp_clock <= #1 timestamp_clock + 1;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
@@ -274,7 +289,9 @@
.rx_WR_enabled(rx_WR_enabled),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
- .tx_underrun(tx_underrun));
+ .tx_underrun(tx_underrun), .tx_drop(tx_drop),
+ .timestamp_clock(timestamp_clock),
+ .tagline_0(tx_tagline[0]), .tagline_1(tx_tagline[1]) );
`ifdef RX_DUAL
defparam rx_buffer.NUM_CHAN=2;
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