On Mon, Mar 23, 2009 at 11:04 AM, kaleem ahmad <kaleem_...@yahoo.com> wrote:
>
> Thanks Brian,
>
> By cycle time I mean that a transmitter (e.g. FSK, ZigBee or any other) is
> transmitting something (I am not interested what is being transmitted) after
> fixed time intervals let say 50ms. Now this transmitter will continue
> transmitting data after every 50ms. This 50ms is the cycle time.

Keep it in the time domain and just do RSSI estimation.  Then count
the number of samples between high power and no power input.  This
should work well for high SNR situations.  If you need to work in
lower SNR situations, you can perform some other operations on the
signal to detect if there is something there that resembles a digital
signal (an exercise left to the reader).

You definitely don't need to move to the frequency domain and should
probably be avoided.

As for your ADC question, it's just doing filtering with decimation.
The actual ADC sample rate stays the same, but your signal is
digitally filtered and samples thrown away.  The filtering avoids
aliasing that occurs when you throw samples away.

Good luck.

Brian


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