Hello, i have read that the interplation rate set in the GNU Radio Python script is actually a combination of 2 interpolation rate values on the USRP. the AD9860 chips are set by default to interpolate at a value of 4. therefore, the user must select an interpolation rate that is divisible by 4.
can anyone explain how implemented the CIC interploator Filter (how many stages) in the FPGA. if we want a interpolation of 32, the interpolation rate is 4 in the AD9860 (4x interpolation), sothat the interpolation is 32/4=8 in the FPGA (stages ??), am i right? thanks a lot! slimchao -- View this message in context: http://www.nabble.com/CIC-Interpolator-Filter-in-the-FPGA-tp22757289p22757289.html Sent from the GnuRadio mailing list archive at Nabble.com. _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
