On Sun, 10 May 2009, davek wrote:
have you had success with your translating filters ?
dave
Dave-
thanks much for responding. I have not yet succeeded in making my
application work. Let me just review what I am trying to do. I want to
capture with the USRP2 two signals; one AM with a carrier at 1 MHz and a
modulation at 5 kHz. The other unmodulated at 5 kHz. I did realize after
my last posting that my decimation in the FPGA was too high (sampling rate
too low) to capture the bandwidth I was interested in, which is (at first
anyway) 1 MHz (since my two center frequencies are separated by about that
much). So I decreased the decimation to give an effective sampling rate
in the FPGA of just over 2 MHz, which should be sufficient to capture
(just barely) the 1 MHz AM signal and the regular one at 5 kHz. However,
I still did not see what I expected. The only thing I am seeing (in
addition to a random spectra in my fft sinks) is "S" printed to the
screen. I'm not sure what this is exactly but it's probably an under-run
error of some kind analogous to the Uu in the USRP1. For completeness, my
new decimation rates are: 48 instead of 128 in the FPGA (gives a sampling
rate of 2.083 MHz instead of 781.25 kHz) and 42 instead of 16 in software
on the host PC to give a final acquisition rate of 49.6 kHz, which is
about what I had previously (I'm interested ultimately in resolving a 5
kHz signal, so I wanted to oversample by a factor of 10). Anyway, I'll
continue to look at my code and see if I can figure out what's going on.
I was just hoping that writing out my approach in detail would reveal (to
myself or to someone on the list) the stupid error that I was previously
overlooking!
Thanks,
eric
On Fri, May 8, 2009 at 3:02 PM, <emat...@nd.edu> wrote:
Hi all-
I have a USRP2 with a LFRX daughterboard. I'm trying to acquire two
channels each at a separate frequency where Ch0 is amplitude
modulated and Ch1 is not. As per suggestions made to me from this list,
to capture two channels at separate frequencies I was
advised to tune the USRP2 to an average frequency and then use
translating filters to capture the band around each frequency
separately. Typically the AM carrier on Ch0 is at about 1 MHz, and the
signal on Ch1 is about 5 kHz. For both channels I'm
interested in no more than 5 kHz of bandwidth.
I'm using svn 10991 with the SD card updated to the latest fpga and
firmware images on a Fedora 10 x86_64 machine. I don't think I'm
doing this correctly since my spectra is all wrong; perhaps somebody can
help me out. First let me post my USRP1 code that does
this, as this was my starting point:
USRP1: options.decim = 128
usrp_decim=options.decim
self.u = usrp.source_c(0, usrp_decim)
self.u.set_dc_offset_cl_enable(int(0),int(15)) # dc removal off
adc_rate = self.u.adc_rate() # 64 MS/s
# Set the decimation in the FPGA
usrp_rate = adc_rate / usrp_decim # 500 kS/s
#set the decimation in software on the host PC
sw_decim = 10
demod_rate = usrp_rate / sw_decim # 50 kS/s
if not self.u.set_nchannels(nchan): #nchan = 2
sys.stderr.write('set_nchannels(%d) failed\n' % (nchan,))
raise SystemExit
self.subdev = self.u.db(0) + self.u.db(1)
if (len(self.subdev) != 6 or
self.u.db(0,0).dbid() != usrp_dbid.LF_RX):
sys.stderr.write('This code requires a Basic Rx board on Side
A\n')
sys.exit(1)
self.u.set_mux(gru.hexint(0xf0f0f1f0))
# deinterleave two channels from FPGA
self.di = gr.deinterleave(gr.sizeof_gr_complex)
# Channelize the signal of interest.
lpf_coeffs = gr.firdes.low_pass (1, # gain
usrp_rate, # sampling rate
demod_rate/2, # passband cutoff
500, # width of
transition band
gr.firdes.WIN_HANN)
self.lpf_0 = gr.fir_filter_fff (sw_decim,lpf_coeffs)
self.lpf_1 = gr.fir_filter_fff (sw_decim,lpf_coeffs)
# Demodulate with classic sqrt (I*I + Q*Q)
self.magblock_0 = gr.complex_to_mag()
# Get real part of Ch1
self.splitter_1 = gr.complex_to_float()
# now wire it all together
self.connect (self.u, self.di)
# Ch 0
self.connect ((self.di,0), self.magblock_0)
self.connect (self.magblock_0, self.lpf_0)
# Ch 1
self.connect ((self.di,1), self.splitter_1)
self.connect ((self.splitter_1,0),self.lpf_1)
etc
Then I define two set_freq functions, one for each subdevice. Ch0 is
tuned to the carrier frequency of the AM signal, Ch1 is tuned
to 0 Hz.
Now, on the USRP2- since I have only one ddc, I can only tune to one
frequency:
options.decim = 128
freq = 1.e6
self.u = usrp2.source_32fc(options.interface, options.mac_addr)
self.u.set_decim(options.decim)
adc_rate = self.u.adc_rate() # 100 MS/s
#set the decimation in the FPGA
input_rate = self.u.adc_rate() / self.u.decim() # 781.25 kS/s
#set the decimation in software on the host PC
sw_decim = 16
demod_rate = input_rate / sw_decim # 48.828 kS/s
# deinterleave four channels from FPGA
self.di = gr.deinterleave(gr.sizeof_gr_complex)
# Channelize the signal of interest.
lpf_coeffs = gr.firdes.low_pass (1, # gain
input_rate, # sampling rate
demod_rate/2, # passband cutoff
500, # width of transition
band
gr.firdes.WIN_HANN)
self.freq_xlating_lpf_0 = gr.freq_xlating_fir_filter_ccf
(sw_decim,lpf_coeffs, freq/2., input_rate)
self.freq_xlating_lpf_1 = gr.freq_xlating_fir_filter_ccf
(sw_decim,lpf_coeffs, -freq/2., input_rate)
self.magblock_0 = gr.complex_to_mag()
self.splitter_1 = gr.complex_to_float()
# Ch 0
self.connect ((self.di,0),
self.freq_xlating_lpf_0,self.magblock_0,self.gain_correction_0)
# Ch 1
self.connect ((self.di,1), self.freq_xlating_lpf_1,
(self.splitter_1,0),self.gain_correction_1)
etc
I then tune the USRP2 to half of my desired frequency, ie 500 kHz. The
other half of the shifting is down in software.
I would suspect any problem to be in my definition of the
gr.freq_xlating_fir_filter_ccf blocks. I assume the sampling frequency is
set to the sampling rate going in to the filter block before decimation.
I am setting the center frequency to be again at half the
desired frequency to shift by that amount.
Any thoughts?
Thanks much,
eric
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