On Tue, Jun 30, 2009 at 10:12, B. Godana<li...@ruby-forum.com> wrote:
> Yes, I want to do that to utilize more bandwidth of the daughter-boards > rather than being limited by the sampling rate of the ADC/DAC. > > But, it looks it is impossible? If you reprogram the USRP(1) FPGA code, you can generate waveforms up to 32 Msps into the AD9862, which uses 1:4 hardware upsampling to get to the 128 Msps of the DAC. Theoretically this gives you 64 MHz of (complex baseband) bandwidth, though the passband of the AD9862 upsampling filter will limit this to about 50 MHz of usable bandwidth. On the receive side, you do get the full 64 MHz downconverted passband, but the anti-aliasing filters on most of the daughterboards will effectively limit this to < 60 MHz. Johnathan _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
