Thank you for the fast reply. It looks like I need the SATA fanout connectors to be the host in this case because pin 2-3 are TX for the SATA port. Would there be any issue having the mini-SAS as the target? (part: iSAS-7P88-U)
Charles On Mon, Dec 7, 2009 at 2:29 PM, Matt Ettus <m...@ettus.com> wrote: > On 12/07/2009 11:17 AM, Charles Irick wrote: >> >> Hello, >> I am narrowing down my issues and I think my problem is related to >> physically connecting the USRP2 to the V5 and it being a host to host >> connection. (I think I have Tx connected to Tx and Rx to Rx) For >> verification, are the A1-A13 pins on top or the B1-B13 pins for the >> mini-SAS port? ( >> http://gnuradio.org/trac/attachment/wiki/USRP2Schem/expansion.pdf ) My >> guess is that the B1-B13 pins are at the top with B1 being in the top >> left corner if you are looking at the port on the front of the USRP2. > > > All outputs are on B, which is on top. > > >> Also, when using two USRP2s you should have this same host to host >> issue, is this resolved because the mimo cable is a crossover? Thanks >> in advance for any help. > > All SAS cables are what you would call crossover. A on one side connects to > B on the other. Wiring diagrams are here: > > http://www.cs-electronics.com/isas-cables-NEW.htm > > > >> >> Charles >> >> On Tue, Dec 1, 2009 at 4:30 PM, Matt Ettus<m...@ettus.com> wrote: >>> >>> On 12/01/2009 12:58 PM, Charles Irick wrote: >>>> >>>> Hello, >>>> I'm most likely having a clock issue because I cannot get any data >>>> transfers going between the USRP2 and GTPs on the V5. A few questions: >>>> >>>> - I'm not quite sure I understand the 10MHz reference clock idea, or >>>> its usage; I looked through the HDL and everything on the FPGA is >>>> running at 100MHz. >>> >>> The 10 MHz reference input on the front is optional. If you connect it >>> and >>> enable locking, the 100 MHz main oscillator will lock to it, otherwise it >>> will free run. Everything inside the FPGA runs at 100 MHz (DSP) or 50 >>> MHz >>> (processor). >>> >>> There is also a 10 MHz reference clock sent out on the MIMO connector. >>> When >>> turned on, it will be the 100 MHz clock divided down by 10. >>> >>>> - I assume I will not need to provide this reference clock if the >>>> USRP2 is the driver given that sd_gentest appears to do so in the main >>>> functions clocks_mimo_config. Either way I'm using the SAS to quad >>>> SATA cable so the clock isn't even transferred to the GTPs (literally, >>>> it's supposed to derive it from the data). >>> >>> sd_gentest will generate packets and send them on the serdes on the MIMO >>> cable. You should be able to receive it without using the 10 MHz >>> reference >>> clock because, as you say, the clock is recovered from the data. >>> >>>> - My only clocking options on the GTP's are 150 or 75MHz. I'm not sure >>>> if I should clock the USRP2's FPGA or the reference differently to >>>> match this. >>> >>> >>> The important thing is that you get the GTPs set up for the correct data >>> rate. On the USRP2, the main clock to the SERDES chip is 100 MHz. 2 >>> Bytes >>> are sent on each clock, so the effective data rate is 1.6 Gbps. However, >>> since 8b-10b coding is used, the on the wire bit rate is 2.0 Gbps >>> (20*100MHz). So whatever reference clock you use, you need the GTP to be >>> working at 2 Gbps. I am by no means an expert on the GTPs, but I think >>> the >>> easiest way to do this is to have a reference clock of 100 MHz. >>> >>> You could probably use the PLLs in the V5 to create a 100 MHz reference >>> clock from one of your other clock rates. >>> >>> Matt >>> > > _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio