On Fri, Jan 15, 2010 at 2:07 PM, Eric Blossom <e...@comsec.com> wrote:

>
> Actually, PAUSE handling is all handled in the FPGA.  When the FIFO is
> getting full, a PAUSE frame is sent on the wire telling the host to
> stop sending for a while.
>

Incidentally my System Engineer/Project Lead points out that if the
USRP2 is actually telling the host to stop sending (which certainly
appears to be the case) then we are only able to get overall
throughput with two USRP2s over two gig-e connections comparable to
what we were getting with a single USRP over a single USB 2.0 line.
Something of a disappointment to us.


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