On 04/20/2010 06:22 AM, Matthias Wilhelm wrote:
Hi,
I'm currently working on a few changes to the FPGA image, but I ran
into some strange issues that I want to bring up here.
1. It seems that txrx_edk10.1_3.3git-645-gb811e87.bin from the binary
builds in http://gnuradio.org/releases/usrp2-bin/trunk/ is not
properly working with both the latest provided u2_rev3.bin as well as
a custom build one from the latest git version of the gnuradio
firmware. The hardware boots up, the LEDs flash correctly, and the
find_usrp2 also works, but the usrp2_fft.py seems to work at first,
but the samples provided seem like noise, although in normal
operation signals are visible. Additionally, switching the channel
seems to work as well, but there is just different levels of noise
everywhere. When changing the decimation value from 16 to 4, the fft
(and probably the hardware) hangs. Revision
txrx_edk10.1_3.3git-594-g02616cf8.bin seems to work correctly. Either
I'm doing it wrong, or there are some issues with the firmware. I
tried this with the XCVR2450 board.
The latest version splits out the XCVR2450 support into a separate file,
so you need txrx_xcvr2450.bin
2. The Xilinx tools in version 11.1 are without patches not able to
generate the bitstream, even make proj failed. The build also fails
because it needs more RAM than available with a self-made project.
With the latest service pack (sp 5) the software is able to produce a
.bin file, but not even the LEDs flash with this version. There are a
lot of warnings, so I cannot tell what the problem is, but it seems
that successful compilation is not enough to make it work. I made an
.ise file with make proj and imported it into ISE, so maybe some
vital information got lost in the process, but since the logic is
given i cant understand how something could go wrong here. 10.1 sp3
works correctly as expected. I'm willing to play around with 11.1 a
bit more, so if you have some ideas on how to debug this, I can
invest some time into this.
There are significant bugs in ISE 11.x which prevent proper compilation
of our designs. We can run the 10.x and 11.x builds side by side on our
logic analyzer and show where it goes wrong in 11.x. We have had Xilinx
applications engineers looking into this and they have not been able to
figure out the problem. So for now we unfortunately need to stick with
10.1.03. Maybe the upcoming 12.x version will work better.
Matt
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