On 06/23/2010 05:37 AM, Tim Pearce wrote:
Juha,
> Do I understand correctly that this is similar to gr-gpio? I thought
> VRT allowed separate streams, why are the bits still in the LSB of I
> and Q? Does this also work with UHD?
I'm using pre-UHD/VRT code at the moment - my understanding is the
metadata VRT adds applies to a group of samples, the GPIO streaming lets
you get boolean values associated with specific samples (with some fixed
delay) - I was planning to use it to get a PPS into the PC before
realising I could just use timestamps..
VRT (the protocol) does handle multiple separate streams. Each stream
is tagged with its stream ID.
> How about dual DDC? Any news about dual DDC for usrp2? How easy would
> it be to add this to UHD?
Adding a second DDC to the fpga is not hard. The support for this is
not yet in UHD, but will be.
I was looking into getting two IF streams as I and Q data a few weeks
ago - there is a version of the USRP2 firmware which supports 2 DDC's -
I think it uses slightly different filters - in the USRP2 FPGA code its
under top/u2_rev3_2rx_iad. A mailing list post suggests the Makefiles
need updating to use the new Ethernet code so its probably not suitable
for UHD yet.
In case its helpful to anyone, the quick solution I went for here (given
I'm still struggling to get an old version of Xilinx ISE) was to modify
the firmware to set the BasicRX as a quadrature board and tuning to 0,
which disables the CORDIC bit. This gives you two streams of IF if your
happy with both streams being the same sample rate/untuned.
You no longer need an old version of ISE. You can use 12 now. Just use
the ise12 branch.
Matt
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