On 06/25/2010 01:31 AM, Matt Robert wrote: > Hi guys, > > I have two questions about the USRP's architecture that I have been > unable to answer from looking around. > > 1) I understand that when a daughter board is tuned for Rx, the exact > frequency is not always possible, so the receiver tunes to the nearest > possible frequency and the 'requested' frequency is the sythesized in > the DDC. Coming from a conventional RF background, I don't understand > why the receivers can only tune to specific frequencies - is it > something like resolution in the digital control of the VCO's in the > receiver? (Just my guess) > PLL synthesizers often have a certain minimum resolution, or "step size". It varies by specific daughter-card. That's a very, very, very conventional "problem" to run into. In many communications systems, there's a standard "raster" that systems are set up on. In television, for example, channels are 6MHz wide, so it's no unusual to find 6MHz or 3MHz as a minimum "resolution" for the synthesizer. In amateur radio systems in VHF and above, channels are often 25KHz wide, so you'll find synthesizers with 25KHz or 12.5KHz minimum step-size in the synthesizer.
The downconverter in the DBS_RX for example is designed for DBS (Direct Broadcast Satellite) applications, where 1MHz and wider channel spacings are the norm, so the resolution of the PLL is quite "coarse" compared to what you might find in a HF synthesizer for example. > > 2) What is the raw bandwidth of the output of a daughterboard? The > USRP2 can process a 25MHz wide chunk so I'm guessing its at least as > big as that. > > Cheers, > Matt > > Again, varies by daughter-card. The TV_RX, for example, has a 6MHz-wide IF filter, so you'll *never* get more than 6MHz of useful bandwidth out of it. The DBS_RX has a programmable baseband filter that goes anywhere from a coupla of MHz to 30MHz, depending on programming. -- Marcus Leech Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org
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