On Wed, Aug 25, 2010 at 11:53:02AM +0530, Sanjay Singh wrote: > Hello Eric, > > In USRP1, I don't want AD9862 to use in my application for many reasons. > > Am looking for changing four parallel pipes of ADC's into two parallel pipes > of ADC's(having interleaved IQ as in the case of DAC's). > I need only changes required to be done in FPGA. Although i know that the > ADC data bus to FPGA will have to be clocked twice the sampling rate. > > I believe this may be a minimal change required in the FPGA. > > Can anyone support me for doing this change. > > Regards > Sanjay
Sanjay, I'm sorry that I don't understand exactly what it is that you are trying to do with the ADC path in the AD9862. (Or what you hope to accomplish with this change.) By default we configure the AD9862 so that it's in "Dual Channel Complex ADC Signal mode" (Rev 0 datasheet pg 23, under "RECEIVE APPLICATIONS SECTION"). This puts the I & Q out separate pins on the chip. We do not have the Hilter Filter enabled, so the two streams (I & Q) are effectively independent. (See Figure 6 on pg 22). You could reprogram the AD9862 to put it into "Dual Channel Real ADC Signal mode", but since we're not using the Hilbert Filter these two modes are equivalent. If you want interleaved I & Q, I suggest that you do that in the FPGA, and not by changing the interface between the the AD9862 and the FPGA. Why I say this is because the existing configuration is well tested, and meets all the timing requirements for the interface between the FPGA and the AD9862. If I haven't answered your question, please try asking it again. Eric _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio