On 06/10/2011 06:15 AM, Sergio Benco wrote:
> 
> Dear all, 
> 
>       I've read on the Ettus transceiver daughterboards datasheet that the
> PLL lock time is around 200us, which makes it suitable for some FH
> systems (eg. Bluetooth). 


Having worked on Bluetooth systems in the past, I can tell you that
200us would be marginal at best for hopping time.

I've tried to measure this time (plus any other
> possible latency between the Host and the USRP2) by timestamping a
> sequence of "set_center_freq()" calls that swaps between two different
> frequencies (2.412 GHz and 2.413 GHz) many times in a top_block run
> (using only C++, not Python).
> 
> The resulting measured time values are around 400us using a USRP2 +
> XCVR2450 and a quadcore host. 
> 
> 1) How was the 200us time value measured? 

This is the time between when the PLL starts the frequency change to
when it is finished.  It is highly variable, and affected by numerous
settings in the chip.

> 2) Is it possible to obtain a sustained hopping rate of 1/200us?  

Probably not when the hopping is initiated from the host.

> 3) If yes, how can we get that value?
> 


Initiate the hopping on the device.  This will take some FPGA work on
your part.

Matt

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