Hi all, I have some problems when compile the fpga source. I open uhd-git\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf with quartus II then compile meet a lot of errors which is the path error like that: Error (10054): Verilog HDL File I/O error at rx_buffer.v(25): can't open Verilog Design File "../../firmware/include/fpga_regs_common.v" when I fix the path problem then compile success. but the generated rbf file is different from the one in rbf directory. I use the newest git version.
Regards!
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