> > > 2011/10/27 Marcus D. Leech <mle...@ripnet.com <mailto:mle...@ripnet.com>> > >> >> Well, that sounds like the lazy solution, intermodulation >> products are bad, so just throwing the transmitter power away is >> not what I'd prefer. >> > But what it points to is an *analog* issue, entirely independant > of the CORDIC (which, as I observe, isn't likely involved in the > test cases > at hand here). > > Analog gain elements (including DACs) have operating regions over > which they're linear, and operating regions over which they're not > linear. If you drive any amplifier near its maximum operating > point, it will start to become non-linear to one degree or > another. I'll > let Matt or one of the other engineering folks at Ettus comment > further, but I personally am totally unsurprised when things start to > become non-linear near the nominal maximum operating point. > > > >> Is there any way of finding out what the resolution is? We >> haven't been able to track it down for the RFX2400 board, >> but this sounds like a nice way to test if it _is_ the CORDIC. > > Look at the tune_result_t from tuning: > > > http://files.ettus.com/uhd_docs/doxygen/html/structuhd_1_1tune__result__t.html > > If the actual_dsp_freq is 0, then the CORDIC wasn't involved. > > I tuned to an even number of MHz, which on all of the synthesizers > *should* yield 0 CORDIC frequency. > > But maybe Josh can add a feature to 'uhd_usrp_probe' to display > the PLL resolution (although in some cases, > it may change with target frequency range, I think). > > Thank yo very much for this, It is really usefull, and it furthermore > confirms what we have observed. > At 2.4GHz there is no problems, when we go 300 kHz up, we start > seeing the problems. (see images attached) > > This is further collaborated, with the fact that we can find "good" > frequencies up through the entire band. > Keep in mind also that spur and phase-noise performance of a PLL synthesizer will tend to change with different tunings. Said performance on spot frequencies can be improved by engaging in an optimization exercise involving not only PLL register settings, but changing the analog loop filter on the PLL as well.
-- Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org
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