On 03/23/2012 01:56 PM, Josh Blum wrote:
It just dawned on me, and this may be a good idea in general:
There is a clock sync pin (cgen_sync_b in the fpga top level).
Presumably, a shared PPS could trigger the clock sync signal across
multiple B100. This would synchronously reset the phase across all N
devices. It would require a little FPGA work.
-Josh
Would need to be a one-shot, yes?
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
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