Hey All, I was wondering if there was a way to preload samples onto the FIFO buffer on the FPGA, so that I could theoretically loop through those samples and keep transmitting them? The idea was mentioned in this thread: http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2012-October/005530.html , where the idea was briefly mentioned at the end, however I'm not sure if its actually possible or if anyone has done it before. If it is possible, can someone point me in the right direction?
Thanks, Anisha
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