Hi, I tried to build a simple flow graph of DPSK modulation and demodulation. The result is verified using the Error Rate module. The link shows the flow I'm using.
https://www.dropbox.com/s/jwmmttyi4es4alf/Screenshot%20from%202013-12-03%2021%3A50%3A58.png I know that the output of demod module is unpacked bytes, so an "unpacked to packed" module is attached after demodulation. However, the BER is close to 50%, which surely indicates something wrong. I further analyzed the two inputs of the Error Rate module by writing info to the file sink. It clearly shows the discrepancy. So I just wonder what is wrong with this flow graph. Could someone please help me? Also, as I noticed, in the output file generated after "unpacked to packed" module, there are many consecutive 0s at the start of the file. Does that indicate something? Suggestions are greatly appreciated! Henry
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