Thanks for the answers.

I didn't think that the sine wave in the FPGA were generated with an
integer phase accumulator (I don't know much about how signal processing
is done in FPGAs).  If this is the case, as I understand from Stephen
email, now I know where the frequency error comes from.

On the other hand, I think that the fact that the sine is computed via
the CORDIC method may introduce numerical errors in the amplitude only,
which would not result in a frequency systematic error.

Cheers,
Daniele

On 18/06/2014 00:43, Stephen Harrison wrote:
> Just some quick calculations in python:
> 
> exact phase increment for 10 MHz:
> 
>>>> (10e6/100e6)*2**32
> 429496729.6
> 
> Closest phase increment:
> 
>>>> np.round((10e6/100e6)*2**32)
> 429496730.0
> 
> Resulting frequency:
> 
>>>> (np.round(10e6/100e6*2**32)/2**32)*100e6
> 10000000.009313226
> 
> We are out by 9.3mHz!
> 
> 
> On Tue, Jun 17, 2014 at 3:36 PM, Sylvain Munaut <246...@gmail.com
> <mailto:246...@gmail.com>> wrote:
> 
>     Hi,
> 
>     > To start I want to characterize the phase noise of the device,
>     therefore
>     > I send to both the RX channel and to the frequency reference input the
>     > same 10 MHz signal. I configured the N210 for 200 kHz sampling and a
>     > carrier frequency of 10 MHz.
> 
>     The LFTRX doesn't have a tuner so if you set a carrier freq of 10 MHz
>     the frequency shift is done by the FPGA via CORDIC and  you'll have
>     numerical errors in there. You just can't get rid of them.
> 
> 
>     Cheers,
> 
>        Sylvain
> 
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