Hi Marcus and Johannes, Thanks for your replies!! I fear that I'll have to change platform then -- I was targeting 2 x 9.1428MHz, but this is clearly going to be impossible :( Thanks again and have a nice day! Rob
On Tue, 26 Feb 2019 at 16:35, Müller, Marcus (CEL) <muel...@kit.edu> wrote: > Hi Johannes, Hi Rob, > On Tue, 2019-02-26 at 15:00 +0000, Johannes Demel wrote: > > Hi Rob, > > > > > (1) I cannot set an arbitrary sampling rate (for instance 9.1428M), > but > > > I am required to set e.g. 4M. > > > > USRPs, like every hardware, is constraint in terms of available sampling > > rates. You should stick with power of 2 divides of the master clock > > rate. Otherwise, the CIC filters on the USRP will corrupt your signal. > > > > While that's true, it's omitting the important point, maybe: The E310 > has a very flexible master clock rate. So, from the top of my head, > 9.1428 MHz could be possible, but only if you set the MCR to a multiple > of that first. > > > > (2) even with small sampling rates (like 2M), and despite a 10MB > buffer > > > in between the USRP source and the ZMQ sink, the system keeps > overflowin > > > > That's not very surprising. The Zynq's architecture makes it very hard > to keep both the USRP sample interface and the network interface afloat > at the same time. > > All in all, the E310 has not a great CPU, and what needs to be done > should be done on the E310 until the data rate is really low. > > This might imply that multi-MHz bandwidth applications need FPGA > design. > > Best regards, > Marcus > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio >
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