Hi Johannes,

I try on 2 configurations :

- VM Ubuntu 20.04 + GR 3.9.3.0 + UHD 4.1.0.4

- Native LXubuntu 20.04 Prempt kernel + GR 3.9.4.0 + UHD 4.1.0.4

All are built from sources.

RX SR = 5Msps

TX SR = 200ksps

All seem to be supported by N210. Yes I decimate with the write value (RX SR / TX SR).

On the VM system, I see a lot of underflow that appear randomly. I could measure up to near a second of propagation delay in the flowgraph after 10min working period : it's unusable.

Indeed, working with a native Preempt linux distribution eliminate near all underflow. But sometimes, maybe when OS generates an interrupt with higher priority, I could get one underflow : one underflow in that case in 8H working period. I can accept that if I can reset the flowgraph just after without killing it and restart. The question is how ?

Best regards,

Fabien, F4CTZ.

Le 27/10/2021 à 14:47, Johannes Demel a écrit :
Hi Fabien,

unless this is a very specific issue and you know exactly that your OS is the component that causes an issue, I recommend to stick with your distros generic kernel image.

I'd need more information but my gut feeling tells me that your issue is somehow a 2-clock problem.

So let's start with a few questions about your system.
Which Linux distribution do you use? Which exact GNU Radio and UHD versions do you use? GR 3.9.3? UHD 4.1.0.x? How did you install GNU Radio. Do you run your flowgraph in a VM or smth similar?
UHD RX sample rate?
UHD TX sample rate?
Are both rates supported by your N210?
Does your flowgraph decimate by some integer value?

Which blocks are in between?
Just to get this out of the way, another hardware block such as an audio sink might get you into a 2-clock problem situation. Since you use hardware blocks, I assume you don't use a Throttle block, if so, remove the Throttle block.

Can you share the flowgraph? It might be easiest to just write down the exact blocks.

Are there any custom blocks?

Do you need continuous streaming?

How fast does the delay grow?

A lot of questions, I know. The answers to these questions might help to find your root issue.

Cheers
Johannes



On 26.10.21 21:41, Fabien PELLET wrote:
Hello,

Thanks for the answer Marcus.

OK I understand that. But is there any solution which permits to reset that growing propagation delay ? How to reset the flowgraph buffers without killing the application and restart it ? Is there any method that permits to purge and resync buffers of the flowgraph ?

Even if my application runs on a preempt_rt OS with a good calculation power, I'm not enough good in Linux tweaking to be sure that my application will not have a unusable delay after a long time. So I can accept to loose some time when I catch a PMT message of underflow to reset the sequencer and buffers. But how without killing apps ??

Best regards,
Fabien, F4CTZ

---- Marcus Müller a écrit ----

Hello!


On 26.10.21 16:12, Fabien PELLET wrote:
 >
 > Why that propagation delay is always growing ?
 >

Exactly *becuause* your underflowing.

Your Receive side produces N samples – but too slow at some point, leading to your transmitter needing to "invent" an amount P of samples, because it simply has a fixed
sample rate.

So, now, from the point of view of the transmitter's DAC, N+P sample periods have passed, whereas the receiver's ADC saw N sample periods. This repeats, and every P > 0. Therefore,
the delay is always only growing.

Best regards,
Marcus

options:
  parameters:
    author: osboxes
    catch_exceptions: 'True'
    category: '[GRC Hier Blocks]'
    cmake_opt: '""'
    comment: ''
    copyright: hgjhg
    description: hjhghg
    gen_cmake: 'On'
    gen_linking: dynamic
    generate_options: qt_gui
    hier_block_src_path: '.:'
    id: testcpp
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    output_language: python
    placement: (0,0)
    qt_qss_theme: ''
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    run_command: '{python} -u {filename}'
    run_options: prompt
    sizing_mode: fixed
    thread_safe_setters: '1'
    title: test
  states:
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    coordinate: [8, 8]
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blocks:
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    value: '5000000'
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    coordinate: [184, 12]
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    state: enabled
- name: analog_agc2_xx_0
  id: analog_agc2_xx
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    comment: ''
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- name: fir_filter_xxx_0
  id: fir_filter_xxx
  parameters:
    affinity: ''
    alias: ''
    comment: ''
    decim: '25'
    maxoutbuf: '0'
    minoutbuf: '0'
    samp_delay: '0'
    taps: 
firdes.complex_band_pass_2(1.0,samp_rate,150,3000,samp_rate*0.1,50,window.WIN_BLACKMAN_HARRIS)
    type: ccc
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    nconnections: '1'
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    type: complex
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    coordinate: [632, 224.0]
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    state: enabled
- name: uhd_usrp_sink_0
  id: uhd_usrp_sink
  parameters:
    affinity: ''
    alias: ''
    ant0: '"TX/RX"'
    ant1: '"TX/RX"'
    ant10: '"TX/RX"'
    ant11: '"TX/RX"'
    ant12: '"TX/RX"'
    ant13: '"TX/RX"'
    ant14: '"TX/RX"'
    ant15: '"TX/RX"'
    ant16: '"TX/RX"'
    ant17: '"TX/RX"'
    ant18: '"TX/RX"'
    ant19: '"TX/RX"'
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    ant21: '"TX/RX"'
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    ant23: '"TX/RX"'
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    ant26: '"TX/RX"'
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    ant28: '"TX/RX"'
    ant29: '"TX/RX"'
    ant3: '"TX/RX"'
    ant30: '"TX/RX"'
    ant31: '"TX/RX"'
    ant4: '"TX/RX"'
    ant5: '"TX/RX"'
    ant6: '"TX/RX"'
    ant7: '"TX/RX"'
    ant8: '"TX/RX"'
    ant9: '"TX/RX"'
    bw0: '0'
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    comment: ''
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    lo_export4: 'False'
    lo_export5: 'False'
    lo_export6: 'False'
    lo_export7: 'False'
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    sd_spec0: '"A:AB"'
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    sync: none
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    type: fc32
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    ant1: '"RX2"'
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    ant14: '"RX2"'
    ant15: '"RX2"'
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    ant9: '"RX2"'
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    comment: ''
    dc_offs0: 0+0j
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    dc_offs11: 0+0j
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    iq_imbal_enb30: default
    iq_imbal_enb31: default
    iq_imbal_enb4: default
    iq_imbal_enb5: default
    iq_imbal_enb6: default
    iq_imbal_enb7: default
    iq_imbal_enb8: default
    iq_imbal_enb9: default
    lo_export0: 'False'
    lo_export1: 'False'
    lo_export10: 'False'
    lo_export11: 'False'
    lo_export12: 'False'
    lo_export13: 'False'
    lo_export14: 'False'
    lo_export15: 'False'
    lo_export16: 'False'
    lo_export17: 'False'
    lo_export18: 'False'
    lo_export19: 'False'
    lo_export2: 'False'
    lo_export20: 'False'
    lo_export21: 'False'
    lo_export22: 'False'
    lo_export23: 'False'
    lo_export24: 'False'
    lo_export25: 'False'
    lo_export26: 'False'
    lo_export27: 'False'
    lo_export28: 'False'
    lo_export29: 'False'
    lo_export3: 'False'
    lo_export30: 'False'
    lo_export31: 'False'
    lo_export4: 'False'
    lo_export5: 'False'
    lo_export6: 'False'
    lo_export7: 'False'
    lo_export8: 'False'
    lo_export9: 'False'
    lo_source0: internal
    lo_source1: internal
    lo_source10: internal
    lo_source11: internal
    lo_source12: internal
    lo_source13: internal
    lo_source14: internal
    lo_source15: internal
    lo_source16: internal
    lo_source17: internal
    lo_source18: internal
    lo_source19: internal
    lo_source2: internal
    lo_source20: internal
    lo_source21: internal
    lo_source22: internal
    lo_source23: internal
    lo_source24: internal
    lo_source25: internal
    lo_source26: internal
    lo_source27: internal
    lo_source28: internal
    lo_source29: internal
    lo_source3: internal
    lo_source30: internal
    lo_source31: internal
    lo_source4: internal
    lo_source5: internal
    lo_source6: internal
    lo_source7: internal
    lo_source8: internal
    lo_source9: internal
    maxoutbuf: '0'
    minoutbuf: '0'
    nchan: '1'
    num_mboards: '1'
    otw: ''
    rx_agc0: Default
    rx_agc1: Default
    rx_agc10: Default
    rx_agc11: Default
    rx_agc12: Default
    rx_agc13: Default
    rx_agc14: Default
    rx_agc15: Default
    rx_agc16: Default
    rx_agc17: Default
    rx_agc18: Default
    rx_agc19: Default
    rx_agc2: Default
    rx_agc20: Default
    rx_agc21: Default
    rx_agc22: Default
    rx_agc23: Default
    rx_agc24: Default
    rx_agc25: Default
    rx_agc26: Default
    rx_agc27: Default
    rx_agc28: Default
    rx_agc29: Default
    rx_agc3: Default
    rx_agc30: Default
    rx_agc31: Default
    rx_agc4: Default
    rx_agc5: Default
    rx_agc6: Default
    rx_agc7: Default
    rx_agc8: Default
    rx_agc9: Default
    samp_rate: samp_rate
    sd_spec0: '"A:A"'
    sd_spec1: ''
    sd_spec2: ''
    sd_spec3: ''
    sd_spec4: ''
    sd_spec5: ''
    sd_spec6: ''
    sd_spec7: ''
    show_lo_controls: 'False'
    start_time: '-1.0'
    stream_args: ''
    stream_chans: '[]'
    sync: none
    time_source0: ''
    time_source1: ''
    time_source2: ''
    time_source3: ''
    time_source4: ''
    time_source5: ''
    time_source6: ''
    time_source7: ''
    type: fc32
  states:
    bus_sink: false
    bus_source: false
    bus_structure: null
    coordinate: [149, 438]
    rotation: 0
    state: true

connections:
- [analog_agc2_xx_0, '0', uhd_usrp_sink_0, '0']
- [fir_filter_xxx_0, '0', analog_agc2_xx_0, '0']
- [uhd_usrp_source_1, '0', fir_filter_xxx_0, '0']
- [uhd_usrp_source_1, '0', qtgui_waterfall_sink_x_0, '0']

metadata:
  file_format: 1

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