On Sat, Feb 10, 2024 at 2:14 PM Chris <gayta...@gmail.com> wrote: > All, I am trying to offload some of my processing power onto my X310's > FPGA. I have the environment set up but still find myself confused on how > to build the out of tree block. I was able to add a block and I'm not sure > what to do next? > > > My design process is as follows: Matlab, get HDL code for DSP algorithms, > and deploy it on the RFNOC? > > My goal is to start out with implementing an adaptive filter on the FPGA. > When I looked in the FIR filter .v example I wasn't able to match how this > code works with the rfnoc environment. When I add my new oot block I have > the verilog code similar to the gain block example but not sure what else > needs to be changed besides dropping in the verilog code into the > newly_added_oot_block.v > > Is there any more documentation I can follow to make sure I am following > the right path? > Any pointers would be appreciated! >
This is better asked over at the USRP users mailing list since it's USRP and RFNoC specific: https://lists.ettus.com/list/usrp-users.lists.ettus.com I've got some pointers once you're signed up and ask over there. Brian >
