On Mon, 16 Mar 2020 08:38:04 -0400 Dan Purgert <d...@djph.net> wrote:
> On Mar 15, 2020, tom wrote: > > [...] The biggest technical problem is the > > lack of ASIC northbridge, or rather something to interface the CPU > > to an PCIE bus. Currently the best thing available you can get is > > an FPGA and it is a severe bandwidth bottleneck. It's also super > > expensive getting an FPGA that beefy enough. I don't see RISCV > > going anywhere until this is solved except microcontroller > > applications. > > > > The second problem is patents that prevent RISCV developers from > > implementing a lot of popular specs and standards. Just as an > > example look at the licensing cost of implementing HDMI vs > > DisplayPort. > > On the one hand, I understand why a "large market audience" device > would need HDMI or DisplayPort or the newest whizbang 256K DNA > ("Direct Neural Attachment") adapter is ... but why does that need to > be on a small-market / hobby computer? > > I can only speak for myself, but a reasonably open PC at the $400 mark > would certainly be competitive to dell or hp; even if it were > "limited" in the peripheral interconnect area (assuming, of course, > the motherboard's peripheral layout were well documented and people > were encouraged to make stuff -- see arduino or rpi expansion boards ) > generally you want to be able to attach a video card or high performance disk controller to a PCIE slot. you /can/ do these things with an FPGA but I wouldn't call it very reliable. You do too many things or send too much data over the bus it exceeds the bandwidth and the system locks up needing a reset. -- ____________________________________ / Sed quis custodiet ipsos Custodes? \ | | \ [Who guards the Guardians?] / ------------------------------------ \ \ /\ /\ //\\_//\\ ____ \_ _/ / / / * * \ /^^^] \_\O/_/ [ ] / \_ [ / \ \_ / / [ [ / \/ _/ _[ [ \ /_/ _______________________________________________ Dng mailing list Dng@lists.dyne.org https://mailinglists.dyne.org/cgi-bin/mailman/listinfo/dng