>>
>>
>>
> First of all check your VHDL syntax! There are some errors.
> Create a dummy entity submodule and the instantiation will be documented.
>
>
There were some errors, thanks. However I have another example, this time the
VHDL syntax should be correct:
entity top is
port(
input : in std_logic;
output : out std_logic
);
end top;
architecture behav of top is
component sub
port (
release : in std_logic;
DO : out std_logic_vector(1 downto 0)
);
end component;
begin
end behav;
If the signal is called "release", then the component sub is not processed by
Doxygen. I understand from vhdlscanner.l that Doxygen sees "release" as VHDL
keyword and is therefore confused. But I`ve never seen a VHDL compiler that
doesn`t let me use the name "release".
Regards,
Viktor
------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and
threat landscape has changed and how IT managers can respond. Discussions
will include endpoint security, mobile security and the latest in malware
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
_______________________________________________
Doxygen-users mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/doxygen-users
