I haven't done an extensive look at this, but I've noticed a couple of
things. The 2D driver seems to use a caching scheme for register writes.
Also, at one point I had a nasty lockup trying to switch to a vt from
fullscreen quake, but I haven't tried it with my latest build yet. I've
noticed other drivers have a fullscreen ioctl, but the mach64 currently
does not. It seems that once we have the DMA interface defined, we'll
want the 2D acceleration to use that as well as the locking scheme, right?
Frank, any progress there?
On another note, I'm attaching a small patch to fix a few things.
1. The AGP register setup was using the wrong macro, since the
registers are in Block 1, it should be using outm() instead of outr().
2. I added some defines for the FIFO sizes in GUI_CNTL and moved the
setup to do_dma_init instead of the busmaster test.
3. I did some general cleanup to fix a couple typos and quiet compiler
warnings.
4. The DMA memory allocation used in the busmaster test uses the
interface described in the kernel docs (Documentation/DMA-mapping.txt).
The 2.4.13 kernel adds 64-bit DMA support, so if you have CONFIG_HIGHMEM
defined, dma_addr_t is defined as u64. The code was passing u32 handles
to the allocation/free functions instead of dma_addr_t handles. This bit
me as I have CONFIG_HIGHMEM4G/CONFIG_HIGHMEM set for some reason (wishful
thinking?). I changed this and cast the returned handles to u32 to get
addresses to pass to the card. I think this is OK, since 32-bit DMA is
assumed unless you use pci_set_dma_mask to indicate that the device can do
64-bit.
5. You can ignore the changes in host.def, my .cvsignore wasn't working
for some reason.
Let me know if you see any problems with the patch and I'll try to take a
look at the locking issues, but I think we need Frank's input there too.
--Leif
On Fri, 26 Oct 2001, Manuel Teira wrote:
> Hello.
>
> I was investigating on how to allow both 2D and 3D acceleration in the
> Mach64. So I'm a little confused:
>
> First of all, I looked at the R128 and RADEON drivers and they are only doing
> a DRILock/DRIUnlock in the LeaveVT and EnterVT functions. Does this mean that
> those cards can do 3D and 2D operation at the same time? Then I looked a
> little in the mga 2D driver and a few more locking operations are showed.
> After this, I'm not sure about what we must interlock between 2D and 3D
> operation.
>
> I would like to know what do you think about the following assumptions:
> 1.-The proper function to lock 3D operation from XFree is DRILock.
>
> 2.-We must lock all the operations in the 2D driver that tries:
> Mach64WaitForIdle
> Mach64WaitForFIFO
> to guarantee that the reached FIFO condition is true.
>
> This investigation shows me another funny thing:
> When the 2D Xfree driver only has to make one register write, it doesn't try
> a Mach64WaitForFIFO. Is this correct? If the DRI driver was writing on the
> command FIFO, couldn't the 2D attempt to write on the FIFO fail ? On the
> other hand, when there are more than one register write, say N-register
> writes, the 2D driver makes a Mach64WaitForFIFO(N) before trying to write to
> the registers.
>
>
> Is there any other 2D operation that we should need to lock? What criteria
> must I follow to make this the right way? I suppose that I don't need to lock
> any register write, but I'm not sure, because the FIFO could get full while
> I'm writing from the 2D driver.
>
> I will keep looking to the other drivers, but I would like to have others
> opinions.
>
> On the MESA side, it looks that the hardware locking is already implemented
> through the functions LOCK_HARDWARE and UNLOCK_HARDWARE.
>
>
> Best regards.
>
> --
> Manuel Teira
>
>
>
> _______________________________________________
> Dri-devel mailing list
> [EMAIL PROTECTED]
> https://lists.sourceforge.net/lists/listinfo/dri-devel
>
--
Leif Delgass
? exports
? mach64-patch
? config/cf/.cvsignore
Index: config/cf/host.def
===================================================================
RCS file: /cvsroot/dri/xc/xc/config/cf/host.def,v
retrieving revision 1.29
diff -u -r1.29 host.def
--- config/cf/host.def 2001/08/27 17:43:00 1.29
+++ config/cf/host.def 2001/10/26 18:16:56
@@ -28,7 +28,7 @@
#define BuildXF86DRI YES
-#define HasGlide3 YES
+#define HasGlide3 NO
/* To do profiling of the dynamically loaded 'xyz_dri.so' object, turn
* this on.
@@ -50,10 +50,10 @@
/* #define DoLoadableServer NO */
/* Optionally turn this on to change the place where you install the build */
-/* #define ProjectRoot /usr/X11R6-DRI */
+#define ProjectRoot /usr/X11R6-DRI
/* Optionally turn this on to force the kernel modules to build */
-/* #define BuildXF86DRM YES */
+#define BuildXF86DRM YES
#define XF86AFB NO
Index: programs/Xserver/hw/xfree86/drivers/ati/atidri.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/drivers/ati/Attic/atidri.c,v
retrieving revision 1.1.4.1
diff -u -r1.1.4.1 atidri.c
--- programs/Xserver/hw/xfree86/drivers/ati/atidri.c 2001/10/21 21:08:14
1.1.4.1
+++ programs/Xserver/hw/xfree86/drivers/ati/atidri.c 2001/10/26 18:17:49
@@ -611,7 +611,7 @@
#endif
/* Initialize Mach64's AGP registers */
- cntl = inr( AGP_CNTL );
+ cntl = inm( AGP_CNTL );
cntl &= ~AGP_APER_SIZE_MASK;
switch ( pATIDRIServer->agpSize ) {
case 256: cntl |= AGP_APER_SIZE_256MB; break;
@@ -629,8 +629,8 @@
}
/* Vertex buffers start at AGP offset 0 */
- outr( AGP_BASE, pATIDRIServer->bufferHandle );
- outr( AGP_CNTL, cntl );
+ outm( AGP_BASE, pATIDRIServer->bufferHandle );
+ outm( AGP_CNTL, cntl );
/* Enable bus mastering in PCI config space */
xf86EnablePciBusMaster( pATI->PCIInfo, TRUE );
Index: programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mach64_dma.c
===================================================================
RCS file:
/cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Attic/mach64_dma.c,v
retrieving revision 1.1.4.1
diff -u -r1.1.4.1 mach64_dma.c
--- programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mach64_dma.c
2001/10/21 21:08:15 1.1.4.1
+++ programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mach64_dma.c
+2001/10/26 18:18:08
@@ -161,7 +161,6 @@
DRM_INFO( "\n" );
DRM_INFO( " Z_CNTL = 0x%08x\n", MACH64_READ( MACH64_Z_CNTL ) );
DRM_INFO( " Z_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_Z_OFF_PITCH )
);
- DRM_INFO( " MACH64_PAT_REG0 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG0 )
);
DRM_INFO( "\n" );
}
@@ -169,45 +168,47 @@
static void bm_dma_test(drm_mach64_private_t *dev_priv)
{
struct pci_pool *pool;
+ dma_addr_t table_handle, data_handle;
u32 table_addr, data_addr;
u32 *table, *data;
void *cpu_addr_table, *cpu_addr_data;
int i;
- u32 bus_cntl, src_cntl, gui_cntl, tmp;
DRM_INFO( "Creating pool ... \n");
pool = pci_pool_create( "mach64", NULL, 0x4000,
0x4000, 0x4000, SLAB_ATOMIC );
+ if (!pool) {
+ DRM_INFO( "pci_pool_create failed!\n" );
+ return;
+ }
+
DRM_INFO( "Allocating table memory ...\n" );
- cpu_addr_table = pci_pool_alloc( pool, SLAB_ATOMIC, &table_addr );
- if (!cpu_addr_table) {
+ cpu_addr_table = pci_pool_alloc( pool, SLAB_ATOMIC, &table_handle );
+ if (!cpu_addr_table || !table_handle) {
DRM_INFO( "table-memory allocation failed!\n" );
return;
} else {
table = (u32 *) cpu_addr_table;
+ table_addr = (u32) table_handle;
memset( cpu_addr_table, 0x0, 0x4000 );
}
DRM_INFO( "Allocating data memory ...\n" );
- cpu_addr_data = pci_pool_alloc( pool, SLAB_ATOMIC, &data_addr );
- if (!cpu_addr_data) {
+ cpu_addr_data = pci_pool_alloc( pool, SLAB_ATOMIC, &data_handle );
+ if (!cpu_addr_data || !data_handle) {
DRM_INFO( "data-memory allocation failed!\n" );
return;
} else {
data = (u32 *) cpu_addr_data;
+ data_addr = (u32) data_handle;
}
MACH64_WRITE( MACH64_SRC_CNTL, 0x00000000 );
MACH64_WRITE( MACH64_PAT_REG0, 0x11111111 );
-
- gui_cntl = MACH64_READ( MACH64_GUI_CNTL );
- gui_cntl= ( gui_cntl | 0x00000001 );
- MACH64_WRITE( MACH64_GUI_CNTL, gui_cntl );
- tmp = MACH64_READ( MACH64_GUI_STAT );
- DRM_INFO( "(Before DMA Transfer) PATH_REG0 = 0x%08x\n",
+ DRM_INFO( "(Before DMA Transfer) PAT_REG0 = 0x%08x\n",
MACH64_READ( MACH64_PAT_REG0 ) );
data[0] = 0x000000a0;
@@ -240,8 +241,8 @@
mach64_do_wait_for_idle( dev_priv );
DRM_INFO( "waiting for idle... done.\n" );
- DRM_INFO( "BUS_CNTL = 0x%08x\n", bus_cntl );
- DRM_INFO( "SRC_CNTL = 0x%08x\n", src_cntl );
+ DRM_INFO( "BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) );
+ DRM_INFO( "SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) );
DRM_INFO( "\n" );
DRM_INFO( "data = 0x%08x\n", data_addr );
DRM_INFO( "table = 0x%08x\n", table_addr );
@@ -262,16 +263,17 @@
DRM_INFO( "waiting for idle [locked_after_dma??]...\n" );
if ((i=mach64_do_wait_for_idle( dev_priv ))) {
- DRM_INFO( "resetting engine ... (result=%d)\n", i );
+ DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i);
+ DRM_INFO( "resetting engine ...");
mach64_do_engine_reset( dev_priv );
}
- DRM_INFO( "(Before DMA Transfer) PATH_REG0 = 0x%08x\n",
+ DRM_INFO( "(After DMA Transfer) PAT_REG0 = 0x%08x\n",
MACH64_READ( MACH64_PAT_REG0 ) );
DRM_INFO( "freeing memory.\n" );
- pci_pool_free( pool, cpu_addr_table, table_addr );
- pci_pool_free( pool, cpu_addr_data, data_addr );
+ pci_pool_free( pool, cpu_addr_table, table_handle );
+ pci_pool_free( pool, cpu_addr_data, data_handle );
pci_pool_destroy( pool );
DRM_INFO( "returning ...\n" );
}
@@ -363,16 +365,21 @@
DRM_INFO( "init->fb = 0x%08x\n", init->fb_offset );
DRM_INFO( "init->mmio_offset = 0x%08x\n", init->mmio_offset );
- DRM_INFO( "mmio->offset=0x%08X mmio->handle=0x%08X\n",
- dev_priv->mmio->offset, dev_priv->mmio->handle );
+ DRM_INFO( "mmio->offset=0x%08lx mmio->handle=0x%08lx\n",
+ dev_priv->mmio->offset, (unsigned long) dev_priv->mmio->handle );
+ DRM_INFO( "buffers->offset=0x%08lx buffers->handle=0x%08lx\n",
+ dev_priv->buffers->offset, (unsigned long) dev_priv->buffers->handle
+);
tmp = MACH64_READ( MACH64_BUS_CNTL );
tmp = ( tmp | 0x08000000 ) & ~MACH64_BUS_MASTER_DIS;
MACH64_WRITE( MACH64_BUS_CNTL, tmp );
-
- MACH64_WRITE( MACH64_GUI_CNTL, 0 );
- tmp = MACH64_READ( MACH64_GUI_STAT );
+
+ tmp = MACH64_READ( MACH64_GUI_CNTL );
+ MACH64_WRITE( MACH64_GUI_CNTL, ( ( tmp & ~MACH64_CMDFIFO_SIZE_MASK ) \
+ | MACH64_CMDFIFO_SIZE_128 ) );
+ DRM_INFO( "GUI_STAT=0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) );
+ DRM_INFO( "GUI_CNTL=0x%08x\n", MACH64_READ( MACH64_GUI_CNTL ) );
bm_dma_test( dev_priv );
return 0;
Index: programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mach64_drv.h
===================================================================
RCS file:
/cvsroot/dri/xc/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Attic/mach64_drv.h,v
retrieving revision 1.1.4.1
diff -u -r1.1.4.1 mach64_drv.h
--- programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mach64_drv.h
2001/10/21 21:08:15 1.1.4.1
+++ programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mach64_drv.h
+2001/10/26 18:18:12
@@ -261,6 +261,10 @@
#define MACH64_GUI_CMDFIFO_DEBUG 0x0170
#define MACH64_GUI_CMDFIFO_DATA 0x0174
#define MACH64_GUI_CNTL 0x0178
+# define MACH64_CMDFIFO_SIZE_MASK 0x000000fful
+# define MACH64_CMDFIFO_SIZE_192 0x00000000ul
+# define MACH64_CMDFIFO_SIZE_128 0x00000001ul
+# define MACH64_CMDFIFO_SIZE_64 0x00000010ul
#define MACH64_GUI_STAT 0x0738
# define MACH64_GUI_ACTIVE (1 << 0)
#define MACH64_GUI_TRAJ_CNTL 0x0730
