On 2002.04.26 20:17 Leif Delgass wrote:
> First off, I haven't checked this in yet, because I need to do some
> cleanup, but I've got synchronous DMA working for vertex buffers on both
> AGP and PCI (PCI for me meaning with agpgart unloaded).  Unfortunately,
> at
> the moment it's actually slower than MMIO, since it's synchronous (wait
> for idle at the end of every pass) and there's the overhead of the
> descriptor table setup.

This is great news! Great work Leif!

> So I guess the next thing to do will be to figure out the buffer aging.
> 

mmm.. I think that we should wait until this weekend to checkout Frank's 
interrupt model before we get into too much details with buffer aging.

Instead of doing buffer aging, perhaps we could just shift the engine idle 
wait to before submitting the DMA buffer and leave the DMA buffer running 
while we returned control to the client. This way we could experience some 
concurrency.

We also need to workout the texture uploads to see if we can address the 
VT switching & locking issues.

> I set up the descriptor table in PCI space using the pci_pool interface
> that the bus master test used, and I keep the handles in dev_priv.  It
> took me awhile to figure out how to properly pass the physical address of
> the buffers to the card.  What I'm doing for pci is using:
> 
> address = (u32) virt_to_phys((void *)buf->address)
> 
> and for AGP:
> 
> address = (u32) buf->bus_address
> 
> and to get a valid pointer for reading/writing the buffer with PCI I use:
> 
> u32 *p = (u32 *) buf->address
> 
> Jose, you almost had it before, it's just a matter of using the right
> types and cast.  I'll try and send you a patch soon when I get things
> cleaned up a bit.

It's good that you worked it out and PCI is no longer broken. Nevertheless 
I still want to get to the bottom of this issue as I feel unconfortable 
with the inconsistency between the different PCI and AGP/PCI-GART 
treatement everywhere.

> 
> --
> Leif Delgass
> http://www.retinalburn.net
> 

José Fonseca

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