A while ago I added the stuff to the config/cf/* to enable USE_SSE_ASM
on FreeBSD, but today found that it wasn't enabled on my athlon. I
added the proper sysctl check for it, but it still wasn't enabled. It
turns out the Athlon's extended CPUID function has most of the same
feature bits as the standard CPUID features function, but it doesn't
ever enable the SSE bit. I've made a patch that ORs in the bit from the
standard function, enabling SSE on new Athlons. It's attached.
However, most of the demos I ran saw no improvement from this. The
exception was texcyl, which had an almost negligible but consistent
improvement. This is with a Radeon 7500, RADEON_NO_TCL=1. Are there
any demos in particular that would stress the code that's enabled with
sse that isn't masked out by 3dnow (transforms of normals?)? The total
difference on texcyl between sse/3dnow and no sse/3dnow was on the order
of 1%, so it was a poor benchmark to use.
Anyone opposed to me committing?
--
Eric Anholt <[EMAIL PROTECTED]>
http://people.freebsd.org/~anholt/dri/
Index: extras/Mesa/src/X86/common_x86.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/extras/Mesa/src/X86/common_x86.c,v
retrieving revision 1.14
diff -u -r1.14 common_x86.c
--- extras/Mesa/src/X86/common_x86.c 16 Mar 2002 16:52:57 -0000 1.14
+++ extras/Mesa/src/X86/common_x86.c 11 Jul 2002 08:10:27 -0000
@@ -37,6 +37,10 @@
#if defined(USE_SSE_ASM) && defined(__linux__)
#include <signal.h>
#endif
+#if defined(USE_SSE_ASM) && defined(__FreeBSD__)
+#include <sys/types.h>
+#include <sys/sysctl.h>
+#endif
#include "context.h"
#include "common_x86_asm.h"
@@ -212,8 +216,16 @@
message( "Cannot test OS support for SSE, disabling to be safe.\n" );
_mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
#endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
+#elif defined(__FreeBSD__)
+ {
+ int ret, len, enabled;
+ len = sizeof(enabled);
+ ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0);
+ if (ret || !enabled)
+ _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
+ }
#else
- /* Do nothing on non-Linux platforms for now.
+ /* Do nothing on other platforms for now.
*/
message( "Not testing OS support for SSE, leaving enabled.\n" );
#endif /* __linux__ */
Index: extras/Mesa/src/X86/common_x86_asm.S
===================================================================
RCS file: /cvsroot/dri/xc/xc/extras/Mesa/src/X86/common_x86_asm.S,v
retrieving revision 1.11
diff -u -r1.11 common_x86_asm.S
--- extras/Mesa/src/X86/common_x86_asm.S 14 Jun 2002 03:55:06 -0000 1.11
+++ extras/Mesa/src/X86/common_x86_asm.S 11 Jul 2002 08:10:27 -0000
@@ -133,6 +133,15 @@
* information after we verify that the extended functions are
* supported.
*/
+ /* The features we need are almost all in the extended set. The
+ * exception is SSE enable, which is in the standard set (0x1).
+ */
+ MOV_L ( CONST(0x1), EAX )
+ CPUID
+ TEST_L ( EAX, EAX )
+ JZ ( LLBL (cpuid_failed) )
+ MOV_L ( EDX, ESI )
+
MOV_L ( CONST(0x80000000), EAX )
CPUID
TEST_L ( EAX, EAX )
@@ -141,6 +150,10 @@
MOV_L ( CONST(0x80000001), EAX )
CPUID
MOV_L ( EDX, EAX )
+
+ AND_L ( CONST(0x02000000), ESI ) /* OR in the SSE bit */
+ OR_L ( ESI, EAX )
+
JMP ( LLBL (cpuid_done) )
LLBL(cpuid_other):
