On Mon, 2003-02-03 at 15:02, Keith Whitwell wrote:
> >
> > -#define COMMIT_RING() do { \
> > - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
> > +#define COMMIT_RING() do { \
> > + /* read from PCI bus to ensure correct posting */ \
> > + RADEON_READ( RADEON_CP_RB_WPTR ); \
> > + RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
> > + RADEON_READ( RADEON_CP_RB_WPTR ); \
> > } while (0)
>
> Ouch. Put a conditional around that at least, so that not everybody suffers...
PCI posting applies to all platforms. However I'm trying to understand what this
is trying to do. The final read has an effect in that it ensures that the WPTR is
written not left posted for an undefined time. What does the previous one achieve.
Is there some kind of synchronization requirement against the GART/main memory ?
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