On Thu, Feb 27, 2003 at 10:19:46AM +0000, José Fonseca wrote:
> In the meanwhile I'm going to look to Utah-GLX Savage4 driver to get a
> grasp of what DMA works there so that, een though they just use MMIO
> internally, we get the DRM interfaces right from the beginning.
Ok. I've been through the specs, the Utah-GLX Savage3D OpenGL driver,
and the XFree86 2D Savage drivers and this are my notes about the Savage
chips DMA operation.
1. As usual, at first level you have MMIO, which can access to all
register.
2. Then you have BCI (Burst Command Interface - not BCE, sorry), which
can access to a subset of the registers. Basically it consists a memory
region in the MMIO range where one performs consecutives writes (the
exact address is not important, as long as the writes are consecutive)
which are then sent to the FIFO or, if the FIFO is full, to a circular
buffer on the framebuffer (which can be as big as 1MB). IRQ's can be
generated with the BCI is idle.
BCI is already used in Xfree86 for XAA and almost everything but
setting up the mode.
Although you can send vertex data through the BCI, it's not appropriate
to expose it to the clients since, at least with the Savage4, since it
can perform bus mastering (see below).
3. With MMIO and/or BCI, one can perform bus mastering. It can
read/write from the system-memory/AGP/framebuffer. The operations can be
blits, command data, or vertex data.
I don't know if this is possible with older versions of the Savage
chips - at least this isn't used in the Utah GLX Savage3D driver, so I
suspect not.
Considering the details above, for DMA operation we should:
1) chips with bus mastering:
- disable the BCI overflow circular buffer; or alternatively put it
in the end of the framebuffer and do not map it to the clients.
- clients fill vertex buffers, send to DRM, which initiates the bus
mastering via the BCI.
2) chips without bus mastering:
2.a) BCI is safe:
- enable the BCI overflow circular buffer, and with a generous
ammount of memory.
- clients send state and vertex data directly to the BCI
2.b) BCI is unsafe:
- enable the BCI overflow circular buffer, and with a generous
ammount of memory, but not map it into client space.
- clients fill vertex buffers (in non-DMA'ble memory), asks DRM to
copy into the BCI
Things still to figure out:
- format of the command & vertex data streams for the bus mastering.
- more details about BCI
These probably are answered in the BCI reference manual which I don't
have.
José Fonseca
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