On Sat, 31 May 2003, Leif Delgass wrote:
> Here's some more info on HOSTDATA:
> In MMIO/pseudo-DMA mode, when we see a descriptor with BM_HOSTDATA as the
> GUI master target register (rather than BM_ADDR), we feed the blit data to
> the card through the HOST_DATA[0-15] registers, so it's still MMIO. The
> thing we have to be careful of is that you can't wait for idle between
> writes that set up the blit and the writes of the blit data to the
> HOST_DATA registers, or else the engine will lock up. That's what the
> "no_idle_wait" flag is for in the pseudo-DMA dispatch code. The docs say
> that full FIFO discliple must be maintined when writing to the HOST_DATA
^^^^^^^^^
discipline, that is. I need more coffee. ;)
> registers, which means checking for enough FIFO entries. The registers
> are sequential, so you can do an assembly optimized memcpy of 16 32-bit
> words at a time, checking the fifo between copies. When doing DMA to
> BM_HOSTDATA, the assumption is that the engine takes care of FIFO
> discipline (BM_HOSTDATA isn't really documented well). At any rate, this
> doesn't apply to gears since it doesn't use textures.
--
Leif Delgass
http://www.retinalburn.net
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