On Mon, Oct 27, 2003 at 03:14:11PM +0000, Keith Whitwell wrote:
Jeff Garzik wrote:
Thank you for saying it. This is what I have been preaching (quietly) for years -- command submission and synchronization (and thus, DMA/irq handling) needs to be in the kernel. Everything else can be in userspace (excluding hardware enable/enumerate, of course).
To enable secure direct rendering on current hardware (ie without secure command submission mechanisms), you need command valididation somewhere. This could be a layer on top of the minimal dma engine Linus describes.
Certainly.
Graphics processors are growing more general, too -- moving towards generic vector/data processing engines. I bet you'll see an optimal model emerge where you have some sort of "JIT" for GPU microcode in userspace.
You mean like the programmable fragment and vertex hardware that has been in use for a couple of years now?
I mean, taking current fragment and vertex processing and making it even _more_ general. Which has already happened, on one particular chip maker's chip...
I think that generally you can view all the current generation of hardware as arbitary programmable devices, and most of the graphics drivers are doing code-generation for that hardware on the fly. This isn't exactly new ground for graphics drivers as graphics hardware has alternated (I'm told) between fixed function and programmable cores multiple times now.
In addition, graphics drivers have been doing on-the-fly codegen for the host cpu since year dot. The orignal software-rasterization SGI opengl drivers for windows were supposed to be pretty much state of the art in this respect.
Now that the barriers for codegen have lowered so dramatically (see, eg. http://fabrice.bellard.free.fr/tcc/), it is now feasible to talk of building a code-generating software rasterizer for mesa.
Keith
Keith
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