> radeon/r200 have some 32 Byte alignment restrictions for all textures), though > I just noticed a small error in the patch: > > + case MESA_FORMAT_RGB_DXT1: > + t->texelBytes = 2; > + textureFormat = (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1); > + break; > + case MESA_FORMAT_RGBA_DXT1: > + case MESA_FORMAT_RGBA_DXT3: > + t->texelBytes = 4; > + textureFormat = (MAPSURF_COMPRESSED | MT_COMPRESS_DXT2_3); > + break; > > RGBA_DXT1 (if it works correctly or not is a different matter) almost > certainly needs to be set to the same values as RGB_DXT1 to get at least > somewhat correct results. > Also, if texelBytes is used to calculate memory addresses (like mipmap > offsets), then the results will be very wrong (since the average texelBytes > for RGB_DXT1 and RGBA_DXT1 is just 0.5, for RGBA_DXT3 and RGBA_DXT5 it's 1).
the code that works out the offsets and stuff is bogus for the i830 with compressed textures... I've no idea what it should look like really :-) the intel hardware stores things differently than other things, and relies on the pitch and stuff.. I've no docs (and the NDA my company is under may not cover em :-), I'll try and extrapolate logically from the i810 documentation what a sane person would do.. then I'll try random insane things.. Dave. -- David Airlie, Software Engineer http://www.skynet.ie/~airlied / airlied at skynet.ie pam_smb / Linux DECstation / Linux VAX / ILUG person ------------------------------------------------------- This SF.Net email is sponsored by the new InstallShield X. >From Windows to Linux, servers to mobile, InstallShield X is the one installation-authoring solution that does it all. Learn more and evaluate today! http://www.installshield.com/Dev2Dev/0504 -- _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
