Michel DÃnzer wrote:
On Fri, 2004-10-15 at 15:16 -0700, Eric Anholt wrote:
On Fri, 2004-10-15 at 14:55, Michel DÃnzer wrote:
On Thu, 2004-10-14 at 12:29 +0200, Thomas HellstrÃm wrote:
is DRM_WRITEMEMORYBARRIER() the right way to make sure data has been
flushed to AGP memory before firing it off to the DMA engine?
I think so, assuming DRM_WRITEMEMORYBARRIER boils down to an instruction
with the LOCK prefix.
... which it doesn't (everywhere), looking at
linux/include/asm-i386/system.h and drm/bsd/drm_os_*.h. From my reading
of the Intel manuals, a DRM_MEMORYBARRIER() is needed instead (as the
radeon DRM uses, among the other stuff) to ensure flushing of WC buffers
on all IA-32 CPUs. (I think the WRITEMEMORYBARRIER happens to work on
newer CPUs on Linux because it boils down to an mfence there).
On Radeon the WRITEMEMORYBARRIER wasn't sufficient, and we're doing a
read from the register before the commit of the ring write pointer,
Actually, we're reading the system memory copy of the ring rptr.
supposedly due to some PCI write posting interaction that caused hangs.
Might be related to this issue, might not, or it might have been some
other issue and that extra read isn't necessary any more. Just throwing
this out there.
This was discussed around
http://marc.theaimsgroup.com/?l=dri-devel&m=104429274716412&w=2
, but I must admit I still don't understand 100% why anything would be
needed before the ring wptr update with PCI - IMHO cache coherency
should ensure data integrity no matter when the wptr update really
happens? Maybe the hangs were actually caused by motherboard chipset or
even CPU bugs related to CPU cache writebacks triggered by PCI
transactions? If anybody really really knows what's going on, please
speak up. :\
Don't look at me... The code worked fine for me before that change.
Keith
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