On Sun, 2005-03-13 at 23:40 -0500, Jon Smirl wrote: > On Mon, 14 Mar 2005 15:07:26 +1100, Paul Mackerras <[EMAIL PROTECTED]> wrote: > > [EMAIL PROTECTED] removed from CC since I can't post to it. > > > > Jon Smirl writes: > > > > > It shouldn't hurt to have a parallel non-cached mapping being used in > > > conjuction with this protocol. By definition the non-cached mapping > > > never gets into an inconsistent state. > > > > According to the PowerPC Architecture specification, it is a > > programming error to have both cacheable and uncacheable mappings of > > the same page. That means the hardware designers consider that they > > don't have to worry if the hardware misbehaves if software does > > that. :P So that is not a feasible solution for us. > > > > Paul. > > Ok, I see this is a problem for the PPC. I've never used a PPC so you > guys have to tell me what is illegal on it.
And probably for other platforms as well. I'm pretty sure some Athlons will be very upset too. I'm not even sure you can do that sort of tricks on MIPS which has strange mapping rules, etc, etc, etc... Anyway, mixing cacheable and non-cacheable mappings is asking for trouble, just don't do it. Having the ability to do both (selected by the platform type, or some AGP errata bit, or whatever) is a different issue and might be worth investigating. Ben. ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_id=6595&alloc_id=14396&op=click -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
