On Sun, 24 Jul 2005, Alex Deucher wrote:
> PCIE is not currently working. So for the moment, PCIE cards will not
> work. What you can try is setting up the card with the fglrx driver
> and getting that working then use the radeon register dump scripts in
> r300 cvs to dump the PCIE config and then compare that to how the regs
> get set up in the open drm.
Attached are dumps with fglrx loaded, before X was started and after
it. Card is "X700 Pro". What should I be looking from the dumps?
For some reason if I start X after boot with fglrx, machine hangs,
but if I start X once with the xorg radeon driver, and then switch
back to fglrx, it starts working.
--j
Found Radeon All-in-Wonder at 2:0.0
memory_aperture=0xc0000000
register_aperture=0xdfef0000
DEVICE_ID(0x00000f02): 0x00075e4b=.^K
VENDOR_ID(0x00000f00): 0x5e4b1002=^K..
Dump of PCIE indirect registers starting from 0
0xffffffff 0x1e040000 0x06620663 0x00900003
0x00000000 0x00000000 0x00000000 0x00001004
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00001f00 0x00040100 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x400a1807 0x00000000 0x00000000 0x00000000
0x00000000 0x3b24cf74 0xdfef0f00 0x0010000f
0x00000001 0x00000000 0x00000000 0x00001fd2
0x00000000 0x00001fd2 0x0000e26a 0x0021006b
0x00000000 0x00001004 0x00000010 0x00000000
0x00000000 0x00140000 0x0000073c 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000002 0x00000000 0x00000006 0x00000000
0x00000000 0x20212210 0x0d0e0f10 0x06080c30
0x01020305 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x33330001 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x046e0b93 0x0818010f 0x0818010f 0x003ffff5
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00620000 0x3ab076b1 0x00000000
0x97380000 0x01d5ed08 0x84413ce0 0x00400000
0x80241801 0x00000000 0x007f0000 0x1efe2c80
0x00000000 0x00000000 0x00000000 0x00000000
0x00000001 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000Dump of PLL registers starting from 0
0x00000000 0x0a608015 0x0000bf00 0x0030000c
0x00070086 0x00070097 0x000700e0 0x000700e0
0x00000003 0x00000000 0x013f4004 0x00001a00
0x0400a430 0x00007ffa 0x0400a410 0x00000000
0x00000000 0x00000000 0x001f1212 0x28000200
0x00e16100 0x00000007 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00081c00 0x00003001
M=12 ref_div_src=0
clock 0 : N=134 post_div=7
clock 1 : N=151 post_div=7
clock 2 : N=224 post_div=7
clock 3 : N=224 post_div=7
VCLK_ECP_CNTL=0x00000003
X_MPLL_REF_FB_DIV=0x013f4004
M=4
X_N=64
M_N=63
new_x_mpll_ref_fb_div is computed to be 0x00fafa41
XPLL_CNTL=0x00001a00
new_xpll_cntl is computed to be 0x00001a00
MPLL_CNTL=0x0400a410
new_mpll_cntl is computed to be 0x0400a410
MCLK_CNTL=0x00000000
MEM_CNTL=0x00000069
BUS_CNTL=0x000000fe
MEM_REG1=0x00090008
MEM_REG2=0x00090008
EXT_MEM_CNTL=0x69668234
MEM_INTF_CNTL=0x003f0000
MEM_STR_CNTL=0x0000001f
MEM_INIT_LAT_TIMER=0xf0000000
COMMAND_CNTL=0x00100007=0000 0000 0001 0000 0000 0000 0000 0111
MEMORY_BUFFER_CNTL=0xc7ffc000
DDA_CONFIG_CNTL=0x08800720
DDA_ON_OFF_CNTL=0x30020014
GEN_RESET_CNTL=0x00000000
MEM_SDRAM_MODE_REG=0x10430000
CACHE_LINE=0x00800008
CAP0_BUF0_OFFSET=0x00000000
CAP0_BUF1_OFFSET=0x00000000
CAP0_BUF0_EVEN_OFFSET=0x00000000
CAP0_BUF1_EVEN_OFFSET=0x00000000
AIC_LO_ADDR=0xffffffff
AIC_HI_ADDR=0xffffffff
CP_RB_BASE=0xcdcdcdcc
CP_IB_BASE=0x00000000
AIC_PT_BASE=0xffffffff
AIC_CTRL=0xffffffff
AIC_TLB_ADDR=0xffffffff
AIC_TLB_DATA=0xffffffff
CONFIG_APER0_BASE=0xc0000000
CONFIG_APER1_BASE=0xc8000000
CONFIG_REG1_BASE=0xdfef8000
MEM_BASE=0xc000000c
MC_FB_LOCATION=0xc7ffc000
MC_AGP_LOCATION=0x003f0000
DISPLAY_BASE_ADDR=0xc0000000
OVERLAY_BASE_ADDR=0x00000000
DST_OFFSET=0xc0000000
DST_PITCH=0x00002000
DST_PITCH_OFFSET=0x00000000
SRC_OFFSET=0x00000000
SRC_PITCH=0x00000000
SRC_PITCH_OFFSET=0x00000000
DEFAULT_OFFSET=0x00000000
AGP_BASE=0x00000000
SCRATCH_REG0=0xcdcdcdcd
DAC_CNTL=0xff002002=1111 1111 0000 0000 0010 0000 0000 0010
----------------- Overlay registers ------------------
OV0_SCALE_CNTL= 0x807f0000 = 1000 0000 0111 1111 0000 0000 0000 0000
OV0_REG_LOAD_CNTL= 0x00000010 = 0000 0000 0000 0000 0000 0000 0001 0000
OV0_PITCH0_VALUE=0x00000000
OV0_PITCH1_VALUE=0x00000000
OV0_AUTO_FLIP_CNTL= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_DEINTERLACE_PATTERN= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_STEP_BY= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_P1_H_ACCUM_INIT= 0x20000000 = 0010 0000 0000 0000 0000 0000 0000 0000
OV0_P23_H_ACCUM_INIT= 0x20000000 = 0010 0000 0000 0000 0000 0000 0000 0000
OV0_FILTER_CNTL= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FLAG_CNTL= 0x00000108 = 0000 0000 0000 0000 0000 0001 0000 1000
OV0_H_INC= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_0= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_1= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_2= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_3= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_4= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_BUF0_ADDR=0x00000000
OV0_BUF1_ADDR=0x00000000
OV0_BUF2_ADDR=0x00000000
OV0_BUF3_ADDR=0x00000000
OV0_BUF4_ADDR=0x00000000
OV0_BUF5_ADDR=0x00000000
OV0_P1_X_START_END=0x00000000
OV0_P2_X_START_END=0x00000000
OV0_P3_X_START_END=0x00000000
OV0_SLICE_CNTL= 0x40000000 = 0100 0000 0000 0000 0000 0000 0000 0000
OV0_PIPELINE_CNTL= 0x00000008 = 0000 0000 0000 0000 0000 0000 0000 1000
--------------------- Display merge -------------------
OV0_LIN_TRANS_A= 0x02540408 = 0000 0010 0101 0100 0000 0100 0000 1000
OV0_LIN_TRANS_B= 0x0000175f = 0000 0000 0000 0000 0001 0111 0101 1111
OV0_LIN_TRANS_C= 0x02540408 = 0000 0010 0101 0100 0000 0100 0000 1000
OV0_LIN_TRANS_D= 0x0000175f = 0000 0000 0000 0000 0001 0111 0101 1111
OV0_LIN_TRANS_E= 0x02540408 = 0000 0010 0101 0100 0000 0100 0000 1000
OV0_LIN_TRANS_F= 0x0000175f = 0000 0000 0000 0000 0001 0111 0101 1111
OV0_GAMMA_0_F= 0x01000000 = 0000 0001 0000 0000 0000 0000 0000 0000
OV0_GAMMA_10_1F= 0x01000020 = 0000 0001 0000 0000 0000 0000 0010 0000
OV0_GAMMA_20_3F= 0x01000040 = 0000 0001 0000 0000 0000 0000 0100 0000
OV0_GAMMA_40_7F= 0x01000080 = 0000 0001 0000 0000 0000 0000 1000 0000
OV0_GAMMA_380_3BF= 0x01000700 = 0000 0001 0000 0000 0000 0111 0000 0000
OV0_GAMMA_3C0_3FF= 0x01000700 = 0000 0001 0000 0000 0000 0111 0000 0000
Dump of PCIE remap table 0x00000000 0xc0000000 -3221225472
Found Radeon All-in-Wonder at 2:0.0
memory_aperture=0xc0000000
register_aperture=0xdfef0000
DEVICE_ID(0x00000f02): 0x00075e4b=.^K
VENDOR_ID(0x00000f00): 0x5e4b1002=^K..
Dump of PCIE indirect registers starting from 0
0xffffffff 0x1e000000 0x03f703f8 0x00900003
0x00008100 0x00000000 0x00000000 0x00009004
0x00000010 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000027 0xf8d71000 0x00000000 0xcfff0000
0xf8d71000 0x00000000 0xfcd70000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00001c1e 0x00040100 0xffffffff 0x80000054
0x800001c1 0x80000141 0x8000004c 0x80000134
0x80000068 0x80000145 0x80000150 0x80000148
0x80000149 0x800001b9 0x800001b8 0x80000060
0x80000044 0x80000058 0x80000070 0x800001c0
0x80000135 0x80000055 0x8000019d 0x8000019c
0x80000199 0x8000014c 0x80000154 0x80000144
0x80000198 0x80000045 0x80000140 0x8000002c
0x80000048 0x80000078 0x80000050 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x400a1807 0x00000000 0x00000000 0x00000000
0x00000000 0x0e44a05e 0xdfef0f00 0x0010140f
0x00000001 0x00000000 0x00000000 0x00001fd2
0x00009024 0x000026de 0x0000f63d 0x06750fa9
0x00000000 0x00009004 0x00000010 0x00000000
0x00000000 0x00140000 0x00000ea4 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00010002 0x00000000 0x00000006 0x00000000
0x00000000 0x20212210 0x0d0e0f10 0x06080c30
0x01020305 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x33330001 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x046e0b93 0x0818010f 0x0818010f 0x003ffff5
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00620000 0x32b07eb1 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x007f0000 0x1efc3cad
0x00000000 0x00000000 0x00000000 0x00000000
0x00000001 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000Dump of PLL registers starting from 0
0x00000000 0x0a608015 0x0000bf00 0x006c001b
0x00070086 0x00070097 0x000700e0 0x000401d9
0x00000003 0x00000000 0x013f4004 0x00001a00
0x0400a430 0x00817ffa 0x0400a410 0x00000000
0x00000000 0x00000000 0x001f1212 0xfe000200
0x00e16500 0x00000007 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00081c00 0x00003001
M=27 ref_div_src=0
clock 0 : N=134 post_div=7
clock 1 : N=151 post_div=7
clock 2 : N=224 post_div=7
clock 3 : N=473 post_div=4
VCLK_ECP_CNTL=0x00000003
X_MPLL_REF_FB_DIV=0x013f4004
M=4
X_N=64
M_N=63
new_x_mpll_ref_fb_div is computed to be 0x00fafa41
XPLL_CNTL=0x00001a00
new_xpll_cntl is computed to be 0x00001a00
MPLL_CNTL=0x0400a410
new_mpll_cntl is computed to be 0x0400a410
MCLK_CNTL=0x00000000
MEM_CNTL=0x00000069
BUS_CNTL=0x000000fe
MEM_REG1=0x00090008
MEM_REG2=0x00090008
EXT_MEM_CNTL=0x69668234
MEM_INTF_CNTL=0xffffffc0
MEM_STR_CNTL=0x0000000f
MEM_INIT_LAT_TIMER=0xf0000000
COMMAND_CNTL=0x00100007=0000 0000 0001 0000 0000 0000 0000 0111
MEMORY_BUFFER_CNTL=0xcfffc000
DDA_CONFIG_CNTL=0x08800720
DDA_ON_OFF_CNTL=0x30020014
GEN_RESET_CNTL=0x00000000
MEM_SDRAM_MODE_REG=0x10430000
CACHE_LINE=0x00800008
CAP0_BUF0_OFFSET=0x00000000
CAP0_BUF1_OFFSET=0x00000000
CAP0_BUF0_EVEN_OFFSET=0x00000000
CAP0_BUF1_EVEN_OFFSET=0x00000000
AIC_LO_ADDR=0xffffffff
AIC_HI_ADDR=0xffffffff
CP_RB_BASE=0xf8d71000
CP_IB_BASE=0xf8e91000
AIC_PT_BASE=0xffffffff
AIC_CTRL=0xffffffff
AIC_TLB_ADDR=0xffffffff
AIC_TLB_DATA=0xffffffff
CONFIG_APER0_BASE=0xc0000000
CONFIG_APER1_BASE=0xc8000000
CONFIG_REG1_BASE=0xdfef8000
MEM_BASE=0xc000000c
MC_FB_LOCATION=0xcfffc000
MC_AGP_LOCATION=0xffffffc0
DISPLAY_BASE_ADDR=0xc0000000
OVERLAY_BASE_ADDR=0xc0000000
DST_OFFSET=0xc0000000
DST_PITCH=0x00001400
DST_PITCH_OFFSET=0x00000000
SRC_OFFSET=0xc0000000
SRC_PITCH=0x00001400
SRC_PITCH_OFFSET=0x00000000
DEFAULT_OFFSET=0x54300000
AGP_BASE=0x00000000
SCRATCH_REG0=0x00040c1d
DAC_CNTL=0xff002102=1111 1111 0000 0000 0010 0001 0000 0010
----------------- Overlay registers ------------------
OV0_SCALE_CNTL= 0x80000000 = 1000 0000 0000 0000 0000 0000 0000 0000
OV0_REG_LOAD_CNTL= 0x00000010 = 0000 0000 0000 0000 0000 0000 0001 0000
OV0_PITCH0_VALUE=0x00000000
OV0_PITCH1_VALUE=0x00000000
OV0_AUTO_FLIP_CNTL= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_DEINTERLACE_PATTERN= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_STEP_BY= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_P1_H_ACCUM_INIT= 0x20000000 = 0010 0000 0000 0000 0000 0000 0000 0000
OV0_P23_H_ACCUM_INIT= 0x20000000 = 0010 0000 0000 0000 0000 0000 0000 0000
OV0_FILTER_CNTL= 0x0000000f = 0000 0000 0000 0000 0000 0000 0000 1111
OV0_FLAG_CNTL= 0x00000108 = 0000 0000 0000 0000 0000 0001 0000 1000
OV0_H_INC= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_0= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_1= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_2= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_3= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_FOUR_TAP_COEFF_4= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
OV0_BUF0_ADDR=0x00000000
OV0_BUF1_ADDR=0x00000000
OV0_BUF2_ADDR=0x00000000
OV0_BUF3_ADDR=0x00000000
OV0_BUF4_ADDR=0x00000000
OV0_BUF5_ADDR=0x00000000
OV0_P1_X_START_END=0x00000000
OV0_P2_X_START_END=0x00000000
OV0_P3_X_START_END=0x00000000
OV0_SLICE_CNTL= 0x40000000 = 0100 0000 0000 0000 0000 0000 0000 0000
OV0_PIPELINE_CNTL= 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000
--------------------- Display merge -------------------
OV0_LIN_TRANS_A= 0x12a00000 = 0001 0010 1010 0000 0000 0000 0000 0000
OV0_LIN_TRANS_B= 0x1990190e = 0001 1001 1001 0000 0001 1001 0000 1110
OV0_LIN_TRANS_C= 0x12a0f9c0 = 0001 0010 1010 0000 1111 1001 1100 0000
OV0_LIN_TRANS_D= 0xf3000442 = 1111 0011 0000 0000 0000 0100 0100 0010
OV0_LIN_TRANS_E= 0x12a02040 = 0001 0010 1010 0000 0010 0000 0100 0000
OV0_LIN_TRANS_F= 0x0000175f = 0000 0000 0000 0000 0001 0111 0101 1111
OV0_GAMMA_0_F= 0x01000000 = 0000 0001 0000 0000 0000 0000 0000 0000
OV0_GAMMA_10_1F= 0x01000020 = 0000 0001 0000 0000 0000 0000 0010 0000
OV0_GAMMA_20_3F= 0x01000040 = 0000 0001 0000 0000 0000 0000 0100 0000
OV0_GAMMA_40_7F= 0x01000080 = 0000 0001 0000 0000 0000 0000 1000 0000
OV0_GAMMA_380_3BF= 0x01000700 = 0000 0001 0000 0000 0000 0111 0000 0000
OV0_GAMMA_3C0_3FF= 0x01000700 = 0000 0001 0000 0000 0000 0111 0000 0000
Dump of PCIE remap table 0xcfff0000 0xc0000000 268369920
