Dear DRI/DRM developers, I'm trying to understand the DRM GART interaction with the linux DRM core, because I'm trying to run the M300 Mobility (PCI Express) with Xegl to help out with development. I fetched MESA and DRM, built them (after applying some fixes), and built Xegl.
I'm now trying to run Xegl with a frame buffer, and when starting get [17182196.816000] [drm:radeon_do_init_cp] [17182196.816000] [drm:radeon_do_init_cp] dev_priv->cp_ring->handle e1ca2000 [17182196.816000] [drm:radeon_do_init_cp] dev_priv->ring_rptr->handle e1da3000 [17182196.816000] [drm:radeon_do_init_cp] dev->agp_buffer_map->handle e1da4000 [17182196.816000] [drm] Setting GART location based on old memory map [17182196.816000] [drm:radeon_do_init_cp] dev_priv->gart_size 8388608 [17182196.816000] [drm:radeon_do_init_cp] dev_priv->gart_vm_start 0x4000000 [17182196.816000] [drm:radeon_do_init_cp] dev_priv->gart_buffers_offset 0x4102000 [17182196.816000] [drm:radeon_do_init_cp] Setting phys_pci_gart to 00000000 07FF8000 [17182196.816000] [drm:drm_ati_pcigart_init] PCI: Gart Table: VRAM 07FF8000 mapped at 00000000 [17182196.816000] BUG: unable to handle kernel NULL pointer dereference at virtual address 00000000 (...) Because the driver is said to not work on PCI express cards, I already expected something like this, but I wasn't able to fix it up to now. My problem is that I read various GART interaction code having different code paths depending on whether a) the built-in card is AGP, PCIE or PCI b) the GART table is stored in FB or in MAIN memory I'm specifically puzzled by code relating to b), there is a lot of offset juggling, for instance in radeon_cp.c:radeon_do_init_cp, where for PCI cards the (otherwised unused/0-initialized) mapping.handle is under some circumstances assigned to dev_priv->gart_info.addr, which is then passed to drm_ati_pcigart_init. This code in turn will not malloc the PCIGART table for FB mapping tables, and thus dereference a NULL pointer when trying to memset the 0 address. My problem is now that while I found many articles describing the general idea of DRI and DRM, I could not found papers on the interaction with GART, and the concrete implementation design choices. I don't understand the role of the various offsets, including the fb_offset, radeon_fb_delta and gart_vm_start. An image containing some suggestive base pointer addressing illustrations on what memory areas are used, and where they are located would help me a lot. Maybe I'm just to dumb to grasp more than the big picture, and the code comments should be sufficient, or maybe I missed any docs? -- Christian Neumair <[EMAIL PROTECTED]> ------------------------------------------------------------------------- Using Tomcat but need to do more? Need to support web services, security? Get stuff done quickly with pre-integrated technology to make your job easier Download IBM WebSphere Application Server v.1.0.1 based on Apache Geronimo http://sel.as-us.falkag.net/sel?cmd=lnk&kid=120709&bid=263057&dat=121642 -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
