On 10/26/06, Phillip Ezolt <[EMAIL PROTECTED]> wrote: > Alex, > > I was able to get the latest and greatest of everything compiled and > "limping". X starts up, and then proceeds to consume 100% of the CPU. I > have a good debugging environment, so I'll be able to walk through it with > gdb to figure out exactly what's causing the problem. Once it gets in this > state, I can't kill the X server, and gdb can't attach to it. > > According to oprofile, all of the CPU time is being spent in the kernel on > the "delay_pmtmr" function. > > So it is appears as if we are in the kernel & waiting for something. > > (As an ASIDE, I spent a bunch of time tracing down a stupid kernel panic. If > DRM_MEMORY_DEBUG is defined for the DRM module, drm_ioremap is completely > broken... It will call itself, and eventually cause a panic. ) > > > > > Let us know how it goes! > > > > Alex > > > > > Cheers, > > > --Phil > > > > > > > > > > > > > After looking over the Xorg log files, I discovered differences in the > mappings between the firegl & and the radeon drivers. > > I noticed the maps from both the FireGL driver and radeon driver were very > similar. > > However, there were two differences. > > First, the fglrx driver has an extra entry: > [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) > > Second, the radeon drivers looks like they have broken mappings. > > The MMIO range begins at: 0xb0100000. The last two mappings in the fglrx > driver are within that range. However, in the radeon driver, the are offset > from 0, yet claim to be in I/O space. > > (II) resource ranges after probing: > DRI broken: > [33] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] > [34] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] > ... > fglrx: > [34] 0 0 0xb01203b0 - 0xb01203bb (0xc) IS[B] > [35] 0 0 0xb01203c0 - 0xb01203df (0x20) IS[B] > > 1) What are these mappings used for?
Not sure. Possibly something for PCIE GART? What apertures does the XPRESS chip expose? > 2) Could this incorrect mapping explain the problems that I'm seeing? Possibly. > 3) What part of radeon probe would be responsible for adding these? > RADEONMapMMIO() and RADEONMapFB() set up the register and FB maps and RADEONInitMemoryMap() and friends handle chip side stuff for the memory controller, etc. Sorry I can't be more helpful. Alex > Thanks, > --Phil > > Complete map (Working FGRLX): > (II) resource ranges after preInit: > [0] 0 0 0xb0100000 - 0xb010ffff (0x10000) MX[B] > [1] 0 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B] > [2] -1 0 0xffe00000 - 0xffffffff (0x200000) MX[B](B) > [3] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [4] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [5] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [6] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [7] -1 0 0xb020a400 - 0xb020a4ff (0x100) MX[B] > [8] -1 0 0xb0209800 - 0xb02098ff (0x100) MX[B] > [9] -1 0 0xb0209c00 - 0xb0209cff (0x100) MX[B] > [10] -1 0 0xb020a000 - 0xb020a0ff (0x100) MX[B] > [11] -1 0 0xb0206000 - 0xb0207fff (0x2000) MX[B] > [12] -1 0 0xb0200000 - 0xb0203fff (0x4000) MX[B] > [13] -1 0 0xb0209000 - 0xb02097ff (0x800) MX[B] > [14] -1 0 0xb0204000 - 0xb0205fff (0x2000) MX[B] > [15] -1 0 0xb0003800 - 0xb00038ff (0x100) MX[B] > [16] -1 0 0xb0003400 - 0xb00034ff (0x100) MX[B] > [17] -1 0 0xb0003000 - 0xb00033ff (0x400) MX[B] > [18] -1 0 0xb0002000 - 0xb0002fff (0x1000) MX[B] > [19] -1 0 0xb0001000 - 0xb0001fff (0x1000) MX[B] > [20] -1 0 0xb0000000 - 0xb0000fff (0x1000) MX[B] > [21] -1 0 0xb0100000 - 0xb010ffff (0x10000) MX[B](B) > [22] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [23] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] > [24] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] > [25] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] > [26] 0 0 0x00009000 - 0x000090ff (0x100) IX[B] > [27] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [28] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] > [29] -1 0 0x0000a000 - 0x0000a0ff (0x100) IX[B] > [30] -1 0 0x00008410 - 0x0000841f (0x10) IX[B] > [31] -1 0 0x00008420 - 0x00008420 (0x1) IX[B] > [32] -1 0 0x00008428 - 0x00008428 (0x1) IX[B] > [33] -1 0 0x00008424 - 0x00008424 (0x1) IX[B] > [34] -1 0 0x00008430 - 0x00008430 (0x1) IX[B] > [35] -1 0 0x00008400 - 0x0000840f (0x10) IX[B] > [36] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) > [37] 0 0 0xb01203b0 - 0xb01203bb (0xc) IS[B] > [38] 0 0 0xb01203c0 - 0xb01203df (0x20) IS[B] > > Complete map (Broken DRI): > > (II) resource ranges after preInit: > [0] 0 0 0xb0100000 - 0xb010ffff (0x10000) MX[B] > [1] 0 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B] > [2] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [3] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [4] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [5] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [6] -1 0 0xb020a400 - 0xb020a4ff (0x100) MX[B] > [7] -1 0 0xb0209800 - 0xb02098ff (0x100) MX[B] > [8] -1 0 0xb0209c00 - 0xb0209cff (0x100) MX[B] > [9] -1 0 0xb020a000 - 0xb020a0ff (0x100) MX[B] > [10] -1 0 0xb0206000 - 0xb0207fff (0x2000) MX[B] > [11] -1 0 0xb0200000 - 0xb0203fff (0x4000) MX[B] > [12] -1 0 0xb0209000 - 0xb02097ff (0x800) MX[B] > [13] -1 0 0xb0204000 - 0xb0205fff (0x2000) MX[B] > [14] -1 0 0xb0003800 - 0xb00038ff (0x100) MX[B] > [15] -1 0 0xb0003400 - 0xb00034ff (0x100) MX[B] > [16] -1 0 0xb0003000 - 0xb00033ff (0x400) MX[B] > [17] -1 0 0xb0002000 - 0xb0002fff (0x1000) MX[B] > [18] -1 0 0xb0001000 - 0xb0001fff (0x1000) MX[B] > [19] -1 0 0xb0000000 - 0xb0000fff (0x1000) MX[B] > [20] -1 0 0xb0100000 - 0xb010ffff (0x10000) MX[B](B) > [21] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [22] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) > [23] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) > [24] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) > [25] 0 0 0x00009000 - 0x000090ff (0x100) IX[B] > [26] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [27] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] > [28] -1 0 0x0000a000 - 0x0000a0ff (0x100) IX[B] > [29] -1 0 0x00008410 - 0x0000841f (0x10) IX[B] > [30] -1 0 0x00008420 - 0x00008420 (0x1) IX[B] > [31] -1 0 0x00008428 - 0x00008428 (0x1) IX[B] > [32] -1 0 0x00008424 - 0x00008424 (0x1) IX[B] > [33] -1 0 0x00008430 - 0x00008430 (0x1) IX[B] > [34] -1 0 0x00008400 - 0x0000840f (0x10) IX[B] > [35] -1 0 0x00009000 - 0x000090ff (0x100) IX[B](B) > [36] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) > [37] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) > > ------------------------------------------------------------------------- Using Tomcat but need to do more? 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